dekoder24

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY dekoder24 IS PORT(
    e: IN std_logic;
    a0, a1: IN std_logic;
    y0, y1, y2, y3: OUT std_logic
);
END dekoder24;

ARCHITECTURE arch OF dekoder24 IS
    signal c1,c2: std_logic;
    signal o1,o2,o3,o4: std_logic;
BEGIN
    d1: entity work.dekoder12 port map (e, a1, c1, c2);

    d2: entity work.dekoder12 port map (c1, a0, o1, o2);
    d3: entity work.dekoder12 port map (c2, a0, o3, o4);

    y0 <= o1;
    y1 <= o2;
    y2 <= o3;
    y3 <= o4;

END arch;