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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.NUMERIC_STD.ALL;
- entity ram is
- port (
- register_address : in std_logic_vector(31 downto 0);
- register_write_data : in std_logic_vector(31 downto 0);
- MemWrite : in std_logic;
- MemRead : in std_logic;
- register_output : out std_logic_vector(31 downto 0)
- --debug_write_output : out std_logic_vector(31 downto 0)
- );
- end entity ram;
- architecture dataflow of ram is
- -- Registry Array
- type ram_array is array (0 to 1023) of std_logic_vector(31 downto 0);
- signal registers: ram_array := (others => (others => '0'));
- -- Address to Integer Conversion, REMOVED DUE TO OUT OF BOUNDS SIMULAITON BUG
- --signal Read_Address : integer := 0;
- begin
- -- Debug Outputs
- --debug_write_output <= registers(to_integer(unsigned(register_address)));
- -- Address to Integer Conversion, REMOVED DUE TO OUT OF BOUNDS SIMULAITON BUG
- --Read_Address <= to_integer(unsigned(register_address));
- -- Read Logic
- --register_output <= registers(Read_Address) when MemRead = '1'
- --else (others => '0');
- register_output <= registers(to_integer(unsigned(register_address))) when MemRead = '1'
- else (others => '0');
- -- Write Logic
- registers(to_integer(unsigned(register_address))) <= register_write_data when (MemWrite = '1') and to_integer(unsigned(register_address)) >= 0
- else registers(to_integer(unsigned(register_address)));
- end dataflow;
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