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Mikestriken

RAM

Apr 7th, 2023 (edited)
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VHDL 1.61 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.NUMERIC_STD.ALL;
  4.  
  5. entity ram is
  6.     port (
  7.         register_address     : in std_logic_vector(31 downto 0);
  8.         register_write_data    : in std_logic_vector(31 downto 0);
  9.        
  10.         MemWrite               : in std_logic;
  11.         MemRead               : in std_logic;
  12.        
  13.         register_output  : out std_logic_vector(31 downto 0)
  14.        
  15.         --debug_write_output : out std_logic_vector(31 downto 0)
  16.     );
  17. end entity ram;
  18.  
  19. architecture dataflow of ram is
  20.     -- Registry Array
  21.     type ram_array is array (0 to 1023) of std_logic_vector(31 downto 0);
  22.     signal registers: ram_array := (others => (others => '0'));
  23.    
  24.     -- Address to Integer Conversion, REMOVED DUE TO OUT OF BOUNDS SIMULAITON BUG
  25.     --signal Read_Address : integer := 0;
  26. begin
  27.     -- Debug Outputs
  28.     --debug_write_output <= registers(to_integer(unsigned(register_address)));
  29.  
  30.     -- Address to Integer Conversion, REMOVED DUE TO OUT OF BOUNDS SIMULAITON BUG
  31.     --Read_Address <= to_integer(unsigned(register_address));
  32.  
  33.     -- Read Logic
  34.     --register_output <= registers(Read_Address) when MemRead = '1'
  35.                        --else (others => '0');
  36.     register_output <= registers(to_integer(unsigned(register_address))) when MemRead = '1'
  37.                        else (others => '0');
  38.        
  39.     -- Write Logic
  40.     registers(to_integer(unsigned(register_address))) <= register_write_data when (MemWrite = '1') and to_integer(unsigned(register_address)) >= 0
  41.                                                          else registers(to_integer(unsigned(register_address)));
  42.    
  43. end dataflow;
Tags: Ram
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