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vedic_div32.syr.912b9f90a9

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May 6th, 2015
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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 0.00 secs
  8. Total CPU time to Xst completion: 0.08 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 0.00 secs
  15. Total CPU time to Xst completion: 0.08 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-1-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : YES
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Off
  74. Reduce Control Sets : Off
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 1
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" in Library work.
  115. Entity <vedic_div32> compiled.
  116. Entity <vedic_div32> (Architecture <rtl>) compiled.
  117.  
  118. =========================================================================
  119. * Design Hierarchy Analysis *
  120. =========================================================================
  121. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  122.  
  123.  
  124. =========================================================================
  125. * HDL Analysis *
  126. =========================================================================
  127. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  128. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 31-bit wide.
  129. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 1-bit wide.
  130. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 1-bit wide.
  131. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 30-bit wide.
  132. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 2-bit wide.
  133. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 2-bit wide.
  134. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 29-bit wide.
  135. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 3-bit wide.
  136. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 3-bit wide.
  137. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 28-bit wide.
  138. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 4-bit wide.
  139. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 4-bit wide.
  140. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 27-bit wide.
  141. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 5-bit wide.
  142. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 5-bit wide.
  143. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 26-bit wide.
  144. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 6-bit wide.
  145. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 6-bit wide.
  146. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 25-bit wide.
  147. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 7-bit wide.
  148. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 7-bit wide.
  149. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 24-bit wide.
  150. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 8-bit wide.
  151. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 8-bit wide.
  152. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 23-bit wide.
  153. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 9-bit wide.
  154. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 9-bit wide.
  155. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 22-bit wide.
  156. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 10-bit wide.
  157. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 10-bit wide.
  158. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 21-bit wide.
  159. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 11-bit wide.
  160. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 11-bit wide.
  161. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 20-bit wide.
  162. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 12-bit wide.
  163. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 12-bit wide.
  164. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 19-bit wide.
  165. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 13-bit wide.
  166. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 13-bit wide.
  167. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 18-bit wide.
  168. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 14-bit wide.
  169. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 14-bit wide.
  170. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 17-bit wide.
  171. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 15-bit wide.
  172. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 15-bit wide.
  173. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 16-bit wide.
  174. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 16-bit wide.
  175. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 16-bit wide.
  176. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 15-bit wide.
  177. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 17-bit wide.
  178. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 17-bit wide.
  179. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 14-bit wide.
  180. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 18-bit wide.
  181. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 18-bit wide.
  182. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 13-bit wide.
  183. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 19-bit wide.
  184. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 19-bit wide.
  185. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 12-bit wide.
  186. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 20-bit wide.
  187. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 20-bit wide.
  188. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 11-bit wide.
  189. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 21-bit wide.
  190. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 21-bit wide.
  191. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 10-bit wide.
  192. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 22-bit wide.
  193. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 22-bit wide.
  194. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 9-bit wide.
  195. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 23-bit wide.
  196. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 23-bit wide.
  197. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 8-bit wide.
  198. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 24-bit wide.
  199. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 24-bit wide.
  200. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 7-bit wide.
  201. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 25-bit wide.
  202. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 25-bit wide.
  203. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 6-bit wide.
  204. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 26-bit wide.
  205. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 26-bit wide.
  206. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 5-bit wide.
  207. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 27-bit wide.
  208. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 27-bit wide.
  209. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 4-bit wide.
  210. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 28-bit wide.
  211. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 28-bit wide.
  212. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 3-bit wide.
  213. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 29-bit wide.
  214. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 29-bit wide.
  215. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 2-bit wide.
  216. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 69: Width mismatch. <b_n> has a width of 31 bits but assigned expression is 30-bit wide.
  217. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 30-bit wide.
  218. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 1-bit wide.
  219. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 71: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 31-bit wide.
  220. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 105: Width mismatch. <quo_tmp> has a width of 32 bits but assigned expression is 63-bit wide.
  221. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 106: Width mismatch. <re_tmp> has a width of 32 bits but assigned expression is 63-bit wide.
  222. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 114: Width mismatch. <v_reg.quo_reg> has a width of 32 bits but assigned expression is 63-bit wide.
  223. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 117: Width mismatch. <v_reg.quo_reg> has a width of 32 bits but assigned expression is 63-bit wide.
  224. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 121: Width mismatch. <v_reg.re_reg> has a width of 36 bits but assigned expression is 63-bit wide.
  225. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 123: Width mismatch. <v_reg.re_reg> has a width of 36 bits but assigned expression is 63-bit wide.
  226. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 126: Width mismatch. <v_reg.re_reg> has a width of 36 bits but assigned expression is 63-bit wide.
  227. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  228.  
  229.  
  230. =========================================================================
  231. * HDL Synthesis *
  232. =========================================================================
  233.  
  234. Performing bidirectional port resolution...
  235.  
  236. Synthesizing Unit <vedic_div32>.
  237. Related source file is "/home/calros/enshu3-vedicdivider/vedic_div32.vhd".
  238. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  239. INFO:Xst:1608 - Relative priorities of control signals on register <b_n> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  240. Found finite state machine <FSM_0> for signal <state>.
  241. -----------------------------------------------------------------------
  242. | States | 4 |
  243. | Transitions | 9 |
  244. | Inputs | 3 |
  245. | Outputs | 4 |
  246. | Clock | mclk1 (rising_edge) |
  247. | Reset | state$and0000 (positive) |
  248. | Reset type | synchronous |
  249. | Reset State | fin_state |
  250. | Power Up State | init_state |
  251. | Encoding | automatic |
  252. | Implementation | LUT |
  253. -----------------------------------------------------------------------
  254. WARNING:Xst:737 - Found 36-bit latch for signal <init_reg.re_reg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  255. WARNING:Xst:737 - Found 31-bit latch for signal <b_n>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  256. WARNING:Xst:737 - Found 32-bit latch for signal <init_reg.quo_reg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  257. WARNING:Xst:737 - Found 5-bit latch for signal <init_reg.shift_val>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  258. Found 32-bit register for signal <quo>.
  259. Found 32-bit register for signal <re>.
  260. Found 5-bit register for signal <i>.
  261. Found 5-bit subtractor for signal <i$addsub0000> created at line 133.
  262. Found 32-bit register for signal <k_reg.quo>.
  263. Found 36-bit register for signal <k_reg.re_reg>.
  264. Found 1-bit register for signal <k_reg.re_sign>.
  265. Found 5-bit register for signal <k_reg.shift_val>.
  266. Found 32-bit register for signal <main_reg.quo>.
  267. Found 32-bit addsub for signal <main_reg.quo$mux0000>.
  268. Found 32-bit register for signal <main_reg.quo_reg>.
  269. Found 63-bit comparator greater for signal <main_reg.quo_reg$cmp_gt0000> created at line 111.
  270. Found 32-bit subtractor for signal <main_reg.quo_reg$mux0000>.
  271. Found 1-bit register for signal <main_reg.quo_sign>.
  272. Found 63-bit comparator greater for signal <main_reg.quo_sign$cmp_gt0000> created at line 111.
  273. Found 32x31-bit multiplier for signal <main_reg.quo_sign$mult0000> created at line 105.
  274. Found 36-bit register for signal <main_reg.re_reg>.
  275. Found 63-bit comparator greater for signal <main_reg.re_reg$cmp_gt0000> created at line 121.
  276. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 120.
  277. Found 36-bit addsub for signal <main_reg.re_reg$mux0000>.
  278. Found 1-bit register for signal <main_reg.re_sign>.
  279. Found 5-bit register for signal <main_reg.shift_val>.
  280. Found 32-bit adder for signal <quo$addsub0000> created at line 185.
  281. Found 32x31-bit multiplier for signal <re_tmp$mult0000> created at line 106.
  282. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 106.
  283. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 106.
  284. Found 63-bit shifter logical left for signal <re_tmp$shift0000> created at line 106.
  285. Found 32-bit shifter logical right for signal <tmp_quo_reg$shift0000> created at line 94.
  286. Found 36-bit subtractor for signal <v_re$addsub0000> created at line 184.
  287. Found 36-bit subtractor for signal <v_re$addsub0001> created at line 184.
  288. Found 36-bit subtractor for signal <v_re$addsub0002> created at line 184.
  289. Found 36-bit subtractor for signal <v_re$addsub0003> created at line 184.
  290. Found 36-bit subtractor for signal <v_re$addsub0004> created at line 184.
  291. Found 36-bit adder for signal <v_re$addsub0005> created at line 177.
  292. Found 36-bit subtractor for signal <v_re$addsub0006> created at line 184.
  293. Found 36-bit adder for signal <v_re$addsub0007> created at line 177.
  294. Found 36-bit subtractor for signal <v_re$addsub0008> created at line 184.
  295. Found 36-bit adder for signal <v_re$addsub0009> created at line 177.
  296. Found 36-bit subtractor for signal <v_re$addsub0010> created at line 184.
  297. Found 36-bit adder for signal <v_re$addsub0011> created at line 177.
  298. Found 36-bit adder for signal <v_re$addsub0012> created at line 177.
  299. Found 36-bit subtractor for signal <v_re$addsub0013> created at line 184.
  300. Found 36-bit adder for signal <v_re$addsub0014> created at line 177.
  301. Found 36-bit adder for signal <v_re$addsub0015> created at line 177.
  302. Found 36-bit adder for signal <v_re$addsub0016> created at line 177.
  303. Found 36-bit adder for signal <v_re$addsub0017> created at line 177.
  304. Found 36-bit adder for signal <v_re$addsub0018> created at line 170.
  305. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0000> created at line 183.
  306. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0001> created at line 183.
  307. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0002> created at line 183.
  308. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0003> created at line 183.
  309. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0004> created at line 183.
  310. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0005> created at line 183.
  311. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0006> created at line 183.
  312. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0007> created at line 183.
  313. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0008> created at line 183.
  314. Found 36-bit comparator less for signal <v_re$cmp_lt0000> created at line 176.
  315. Found 36-bit comparator less for signal <v_re$cmp_lt0001> created at line 176.
  316. Found 36-bit comparator less for signal <v_re$cmp_lt0002> created at line 176.
  317. Found 36-bit comparator less for signal <v_re$cmp_lt0003> created at line 176.
  318. Found 36-bit comparator less for signal <v_re$cmp_lt0004> created at line 176.
  319. Found 36-bit comparator less for signal <v_re$cmp_lt0005> created at line 176.
  320. Found 36-bit comparator less for signal <v_re$cmp_lt0006> created at line 176.
  321. Found 36-bit comparator less for signal <v_re$cmp_lt0007> created at line 176.
  322. Found 36-bit comparator less for signal <v_re$cmp_lt0008> created at line 176.
  323. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 173.
  324. Found 32-bit shifter logical left for signal <v_reg.quo$shift0000> created at line 98.
  325. Found 1-bit 32-to-1 multiplexer for signal <v_reg.quo_reg_30$mux0000> created at line 103.
  326. Found 32-bit adder for signal <v_reg0.quo$add0000> created at line 185.
  327. Found 32-bit adder for signal <v_reg0.quo$add0001> created at line 185.
  328. Found 32-bit adder for signal <v_reg0.quo$add0002> created at line 185.
  329. Found 32-bit adder for signal <v_reg0.quo$add0003> created at line 185.
  330. Found 32-bit adder for signal <v_reg0.quo$add0004> created at line 185.
  331. Found 32-bit adder for signal <v_reg0.quo$add0005> created at line 185.
  332. Found 32-bit adder for signal <v_reg0.quo$add0006> created at line 185.
  333. Found 32-bit adder for signal <v_reg0.quo$add0007> created at line 185.
  334. Found 32-bit subtractor for signal <v_reg0.quo$sub0000> created at line 178.
  335. Found 32-bit subtractor for signal <v_reg0.quo$sub0001> created at line 178.
  336. Found 32-bit subtractor for signal <v_reg0.quo$sub0002> created at line 178.
  337. Found 32-bit subtractor for signal <v_reg0.quo$sub0003> created at line 178.
  338. Found 32-bit subtractor for signal <v_reg0.quo$sub0004> created at line 178.
  339. Found 32-bit subtractor for signal <v_reg0.quo$sub0005> created at line 178.
  340. Found 32-bit subtractor for signal <v_reg0.quo$sub0006> created at line 178.
  341. Found 32-bit subtractor for signal <v_reg0.quo$sub0007> created at line 178.
  342. Found 32-bit subtractor for signal <v_reg0.quo$sub0008> created at line 178.
  343. Summary:
  344. inferred 1 Finite State Machine(s).
  345. inferred 250 D-type flip-flop(s).
  346. inferred 41 Adder/Subtractor(s).
  347. inferred 2 Multiplier(s).
  348. inferred 21 Comparator(s).
  349. inferred 32 Multiplexer(s).
  350. inferred 4 Combinational logic shifter(s).
  351. Unit <vedic_div32> synthesized.
  352.  
  353. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
  354.  
  355. =========================================================================
  356. HDL Synthesis Report
  357.  
  358. Macro Statistics
  359. # Multipliers : 2
  360. 32x31-bit multiplier : 2
  361. # Adders/Subtractors : 41
  362. 32-bit adder : 9
  363. 32-bit addsub : 1
  364. 32-bit subtractor : 10
  365. 36-bit adder : 10
  366. 36-bit addsub : 1
  367. 36-bit subtractor : 9
  368. 5-bit subtractor : 1
  369. # Registers : 13
  370. 1-bit register : 3
  371. 32-bit register : 5
  372. 36-bit register : 2
  373. 5-bit register : 3
  374. # Latches : 4
  375. 31-bit latch : 1
  376. 32-bit latch : 1
  377. 36-bit latch : 1
  378. 5-bit latch : 1
  379. # Comparators : 21
  380. 36-bit comparator greatequal : 9
  381. 36-bit comparator less : 9
  382. 63-bit comparator greater : 3
  383. # Multiplexers : 32
  384. 1-bit 31-to-1 multiplexer : 1
  385. 1-bit 32-to-1 multiplexer : 31
  386. # Logic shifters : 4
  387. 32-bit shifter logical left : 1
  388. 32-bit shifter logical right : 1
  389. 36-bit shifter arithmetic right : 1
  390. 63-bit shifter logical left : 1
  391. # Xors : 1
  392. 1-bit xor2 : 1
  393.  
  394. =========================================================================
  395.  
  396. =========================================================================
  397. * Advanced HDL Synthesis *
  398. =========================================================================
  399.  
  400. Analyzing FSM <FSM_0> for best encoding.
  401. Optimizing FSM <state/FSM> on signal <state[1:4]> with one-hot encoding.
  402. ------------------------
  403. State | Encoding
  404. ------------------------
  405. init_state | 0001
  406. main_state | 0100
  407. wait_state | 1000
  408. fin_state | 0010
  409. ------------------------
  410. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
  411. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <32>. This FF/Latch will be trimmed during the optimization process.
  412. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <33>. This FF/Latch will be trimmed during the optimization process.
  413. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <34>. This FF/Latch will be trimmed during the optimization process.
  414. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <35>. This FF/Latch will be trimmed during the optimization process.
  415.  
  416. Synthesizing (advanced) Unit <vedic_div32>.
  417. The following registers are absorbed into accumulator <main_reg.quo>: 1 register on signal <main_reg.quo>.
  418. Unit <vedic_div32> synthesized (advanced).
  419.  
  420. =========================================================================
  421. Advanced HDL Synthesis Report
  422.  
  423. Macro Statistics
  424. # FSMs : 1
  425. # Multipliers : 2
  426. 32x31-bit multiplier : 2
  427. # Adders/Subtractors : 40
  428. 32-bit adder : 9
  429. 32-bit subtractor : 11
  430. 36-bit adder : 10
  431. 36-bit addsub : 1
  432. 36-bit subtractor : 8
  433. 5-bit subtractor : 1
  434. # Accumulators : 1
  435. 32-bit updown loadable accumulator : 1
  436. # Registers : 218
  437. Flip-Flops : 218
  438. # Latches : 4
  439. 31-bit latch : 1
  440. 32-bit latch : 1
  441. 36-bit latch : 1
  442. 5-bit latch : 1
  443. # Comparators : 21
  444. 36-bit comparator greatequal : 9
  445. 36-bit comparator less : 9
  446. 63-bit comparator greater : 3
  447. # Multiplexers : 32
  448. 1-bit 31-to-1 multiplexer : 1
  449. 1-bit 32-to-1 multiplexer : 31
  450. # Logic shifters : 4
  451. 32-bit shifter logical left : 1
  452. 32-bit shifter logical right : 1
  453. 36-bit shifter arithmetic right : 1
  454. 63-bit shifter logical left : 1
  455. # Xors : 1
  456. 1-bit xor2 : 1
  457.  
  458. =========================================================================
  459.  
  460. =========================================================================
  461. * Low Level Synthesis *
  462. =========================================================================
  463. INFO:Xst:2261 - The FF/Latch <35> in Unit <LPM_LATCH_1> is equivalent to the following 4 FFs/Latches, which will be removed : <34> <33> <32> <31>
  464. WARNING:Xst:1293 - FF/Latch <35> has a constant value of 0 in block <LPM_LATCH_1>. This FF/Latch will be trimmed during the optimization process.
  465.  
  466. Optimizing unit <vedic_div32> ...
  467.  
  468. Mapping all equations...
  469. Building and optimizing final netlist ...
  470. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 22.
  471.  
  472. Final Macro Processing ...
  473.  
  474. =========================================================================
  475. Final Register Report
  476.  
  477. Macro Statistics
  478. # Registers : 253
  479. Flip-Flops : 253
  480.  
  481. =========================================================================
  482.  
  483. =========================================================================
  484. * Partition Report *
  485. =========================================================================
  486.  
  487. Partition Implementation Status
  488. -------------------------------
  489.  
  490. No Partitions were found in this design.
  491.  
  492. -------------------------------
  493.  
  494. =========================================================================
  495. * Final Report *
  496. =========================================================================
  497. Final Results
  498. RTL Top Level Output File Name : vedic_div32.ngr
  499. Top Level Output File Name : vedic_div32
  500. Output Format : NGC
  501. Optimization Goal : Speed
  502. Keep Hierarchy : No
  503.  
  504. Design Statistics
  505. # IOs : 130
  506.  
  507. Cell Usage :
  508. # BELS : 7906
  509. # GND : 1
  510. # INV : 2
  511. # LUT2 : 106
  512. # LUT3 : 680
  513. # LUT4 : 775
  514. # LUT5 : 1230
  515. # LUT6 : 2103
  516. # MUXCY : 1506
  517. # MUXF7 : 146
  518. # VCC : 1
  519. # XORCY : 1356
  520. # FlipFlops/Latches : 352
  521. # FD : 164
  522. # FDE : 81
  523. # FDR : 2
  524. # FDS : 6
  525. # LDCP : 99
  526. # Clock Buffers : 2
  527. # BUFG : 1
  528. # BUFGP : 1
  529. # IO Buffers : 129
  530. # IBUF : 65
  531. # OBUF : 64
  532. # DSPs : 8
  533. # DSP48E : 8
  534. =========================================================================
  535.  
  536. Device utilization summary:
  537. ---------------------------
  538.  
  539. Selected Device : 5vlx50tff1136-1
  540.  
  541.  
  542. Slice Logic Utilization:
  543. Number of Slice Registers: 352 out of 28800 1%
  544. Number of Slice LUTs: 4896 out of 28800 17%
  545. Number used as Logic: 4896 out of 28800 17%
  546.  
  547. Slice Logic Distribution:
  548. Number of LUT Flip Flop pairs used: 5030
  549. Number with an unused Flip Flop: 4678 out of 5030 93%
  550. Number with an unused LUT: 134 out of 5030 2%
  551. Number of fully used LUT-FF pairs: 218 out of 5030 4%
  552. Number of unique control sets: 106
  553.  
  554. IO Utilization:
  555. Number of IOs: 130
  556. Number of bonded IOBs: 130 out of 480 27%
  557.  
  558. Specific Feature Utilization:
  559. Number of BUFG/BUFGCTRLs: 2 out of 32 6%
  560. Number of DSP48Es: 8 out of 48 16%
  561.  
  562. ---------------------------
  563. Partition Resource Summary:
  564. ---------------------------
  565.  
  566. No Partitions were found in this design.
  567.  
  568. ---------------------------
  569.  
  570.  
  571. =========================================================================
  572. TIMING REPORT
  573.  
  574. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  575. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  576. GENERATED AFTER PLACE-and-ROUTE.
  577.  
  578. Clock Information:
  579. ------------------
  580. -----------------------------------+------------------------+-------+
  581. Clock Signal | Clock buffer(FF name) | Load |
  582. -----------------------------------+------------------------+-------+
  583. mclk1 | BUFGP | 253 |
  584. divisor<0> | IBUF+BUFG | 99 |
  585. -----------------------------------+------------------------+-------+
  586.  
  587. Asynchronous Control Signals Information:
  588. ----------------------------------------
  589. ---------------------------------------------------------------+---------------------------+-------+
  590. Control Signal | Buffer(FF name) | Load |
  591. ---------------------------------------------------------------+---------------------------+-------+
  592. N0(XST_GND:G) | NONE(init_reg.quo_reg_31) | 1 |
  593. b_n_0__and0000(b_n_0__and00001:O) | NONE(b_n_0) | 1 |
  594. b_n_0__or0000(b_n_0__or00001:O) | NONE(b_n_0) | 1 |
  595. b_n_10__and0000(b_n_mux0031<10>1:O) | NONE(b_n_10) | 1 |
  596. b_n_10__or0000(b_n_10__or00001:O) | NONE(b_n_10) | 1 |
  597. b_n_11__and0000(b_n_11__and00001:O) | NONE(b_n_11) | 1 |
  598. b_n_11__or0000(b_n_11__or00001:O) | NONE(b_n_11) | 1 |
  599. b_n_12__and0000(b_n_12__and00001:O) | NONE(b_n_12) | 1 |
  600. b_n_12__or0000(b_n_12__or00001:O) | NONE(b_n_12) | 1 |
  601. b_n_13__and0000(b_n_13__and00001:O) | NONE(b_n_13) | 1 |
  602. b_n_13__or0000(b_n_13__or00001:O) | NONE(b_n_13) | 1 |
  603. b_n_14__and0000(b_n_14__and00001:O) | NONE(b_n_14) | 1 |
  604. b_n_14__or0000(b_n_14__or00001:O) | NONE(b_n_14) | 1 |
  605. b_n_15__and0000(b_n_15__and00001:O) | NONE(b_n_15) | 1 |
  606. b_n_15__or0000(b_n_15__or00001:O) | NONE(b_n_15) | 1 |
  607. b_n_16__and0000(b_n_mux0031<16>1:O) | NONE(b_n_16) | 1 |
  608. b_n_16__or0000(b_n_16__or00001:O) | NONE(b_n_16) | 1 |
  609. b_n_17__and0000(b_n_17__and00001:O) | NONE(b_n_17) | 1 |
  610. b_n_17__or0000(b_n_17__or00001:O) | NONE(b_n_17) | 1 |
  611. b_n_18__and0000(b_n_18__and00001:O) | NONE(b_n_18) | 1 |
  612. b_n_18__or0000(b_n_18__or00001:O) | NONE(b_n_18) | 1 |
  613. b_n_19__and0000(b_n_mux0031<19>1:O) | NONE(b_n_19) | 1 |
  614. b_n_19__or0000(b_n_19__or00001:O) | NONE(b_n_19) | 1 |
  615. b_n_1__and0000(b_n_1__and00001:O) | NONE(b_n_1) | 1 |
  616. b_n_1__or0000(b_n_1__or00001:O) | NONE(b_n_1) | 1 |
  617. b_n_20__and0000(b_n_mux0031<20>1:O) | NONE(b_n_20) | 1 |
  618. b_n_20__or0000(b_n_20__or00001:O) | NONE(b_n_20) | 1 |
  619. b_n_21__and0000(b_n_mux0031<21>1:O) | NONE(b_n_21) | 1 |
  620. b_n_21__or0000(b_n_21__or00001:O) | NONE(b_n_21) | 1 |
  621. b_n_22__and0000(b_n_mux0031<22>1:O) | NONE(b_n_22) | 1 |
  622. b_n_22__or0000(b_n_22__or00001:O) | NONE(b_n_22) | 1 |
  623. b_n_23__and0000(b_n_23__and00001:O) | NONE(b_n_23) | 1 |
  624. b_n_23__or0000(b_n_23__or00001:O) | NONE(b_n_23) | 1 |
  625. b_n_24__and0000(b_n_24__and00001:O) | NONE(b_n_24) | 1 |
  626. b_n_24__or0000(b_n_24__or00001:O) | NONE(b_n_24) | 1 |
  627. b_n_25__and0000(b_n_25__and00001:O) | NONE(b_n_25) | 1 |
  628. b_n_25__or0000(b_n_25__or00001:O) | NONE(b_n_25) | 1 |
  629. b_n_26__and0000(b_n_26__and00001:O) | NONE(b_n_26) | 1 |
  630. b_n_26__or0000(b_n_26__or00001:O) | NONE(b_n_26) | 1 |
  631. b_n_27__and0000(b_n_27__and00001:O) | NONE(b_n_27) | 1 |
  632. b_n_27__or0000(b_n_27__or00001:O) | NONE(b_n_27) | 1 |
  633. b_n_28__and0000(b_n_28__and00001:O) | NONE(b_n_28) | 1 |
  634. b_n_28__or0000(b_n_28__or00001:O) | NONE(b_n_28) | 1 |
  635. b_n_29__and0000(b_n_29__and00001:O) | NONE(b_n_29) | 1 |
  636. b_n_29__or0000(b_n_29__or00001:O) | NONE(b_n_29) | 1 |
  637. b_n_2__and0000(b_n_2__and00001:O) | NONE(b_n_2) | 1 |
  638. b_n_2__or0000(b_n_2__or00001:O) | NONE(b_n_2) | 1 |
  639. b_n_30__and0000(b_n_30__and00001:O) | NONE(b_n_30) | 1 |
  640. b_n_30__or0000(b_n_30__or00001:O) | NONE(b_n_30) | 1 |
  641. b_n_3__and0000(b_n_3__and00001:O) | NONE(b_n_3) | 1 |
  642. b_n_3__or0000(b_n_3__or00001:O) | NONE(b_n_3) | 1 |
  643. b_n_4__and0000(b_n_4__and00001:O) | NONE(b_n_4) | 1 |
  644. b_n_4__or0000(b_n_4__or00001:O) | NONE(b_n_4) | 1 |
  645. b_n_5__and0000(b_n_5__and00001:O) | NONE(b_n_5) | 1 |
  646. b_n_5__or0000(b_n_5__or00001:O) | NONE(b_n_5) | 1 |
  647. b_n_6__and0000(b_n_6__and00001:O) | NONE(b_n_6) | 1 |
  648. b_n_6__or0000(b_n_6__or00001:O) | NONE(b_n_6) | 1 |
  649. b_n_7__and0000(b_n_7__and00001:O) | NONE(b_n_7) | 1 |
  650. b_n_7__or0000(b_n_7__or00001:O) | NONE(b_n_7) | 1 |
  651. b_n_8__and0000(b_n_8__and00001:O) | NONE(b_n_8) | 1 |
  652. b_n_8__or0000(b_n_8__or00001:O) | NONE(b_n_8) | 1 |
  653. b_n_9__and0000(b_n_mux0031<9>1:O) | NONE(b_n_9) | 1 |
  654. b_n_9__or0000(b_n_9__or00001:O) | NONE(b_n_9) | 1 |
  655. init_reg.quo_reg_0__and0000(init_reg.quo_reg_0__and00001:O) | NONE(init_reg.quo_reg_0) | 1 |
  656. init_reg.quo_reg_0__and0001(init_reg.quo_reg_0__and00011:O) | NONE(init_reg.quo_reg_0) | 1 |
  657. init_reg.quo_reg_10__and0000(init_reg.quo_reg_10__and00001:O) | NONE(init_reg.quo_reg_10) | 1 |
  658. init_reg.quo_reg_10__and0001(init_reg.quo_reg_10__and00011:O) | NONE(init_reg.quo_reg_10) | 1 |
  659. init_reg.quo_reg_11__and0000(init_reg.quo_reg_11__and00001:O) | NONE(init_reg.quo_reg_11) | 1 |
  660. init_reg.quo_reg_11__and0001(init_reg.quo_reg_11__and00011:O) | NONE(init_reg.quo_reg_11) | 1 |
  661. init_reg.quo_reg_12__and0000(init_reg.quo_reg_12__and00001:O) | NONE(init_reg.quo_reg_12) | 1 |
  662. init_reg.quo_reg_12__and0001(init_reg.quo_reg_12__and00011:O) | NONE(init_reg.quo_reg_12) | 1 |
  663. init_reg.quo_reg_13__and0000(init_reg.quo_reg_13__and00001:O) | NONE(init_reg.quo_reg_13) | 1 |
  664. init_reg.quo_reg_13__and0001(init_reg.quo_reg_13__and00011:O) | NONE(init_reg.quo_reg_13) | 1 |
  665. init_reg.quo_reg_14__and0000(init_reg.quo_reg_14__and00001:O) | NONE(init_reg.quo_reg_14) | 1 |
  666. init_reg.quo_reg_14__and0001(init_reg.quo_reg_14__and00011:O) | NONE(init_reg.quo_reg_14) | 1 |
  667. init_reg.quo_reg_15__and0000(init_reg.quo_reg_15__and00001:O) | NONE(init_reg.quo_reg_15) | 1 |
  668. init_reg.quo_reg_15__and0001(init_reg.quo_reg_15__and00011:O) | NONE(init_reg.quo_reg_15) | 1 |
  669. init_reg.quo_reg_16__and0000(init_reg.quo_reg_16__and00001:O) | NONE(init_reg.quo_reg_16) | 1 |
  670. init_reg.quo_reg_16__and0001(init_reg.quo_reg_16__and00011:O) | NONE(init_reg.quo_reg_16) | 1 |
  671. init_reg.quo_reg_17__and0000(init_reg.quo_reg_17__and00001:O) | NONE(init_reg.quo_reg_17) | 1 |
  672. init_reg.quo_reg_17__and0001(init_reg.quo_reg_17__and00011:O) | NONE(init_reg.quo_reg_17) | 1 |
  673. init_reg.quo_reg_18__and0000(init_reg.quo_reg_18__and00001:O) | NONE(init_reg.quo_reg_18) | 1 |
  674. init_reg.quo_reg_18__and0001(init_reg.quo_reg_18__and00011:O) | NONE(init_reg.quo_reg_18) | 1 |
  675. init_reg.quo_reg_19__and0000(init_reg.quo_reg_19__and00001:O) | NONE(init_reg.quo_reg_19) | 1 |
  676. init_reg.quo_reg_19__and0001(init_reg.quo_reg_19__and00011:O) | NONE(init_reg.quo_reg_19) | 1 |
  677. init_reg.quo_reg_1__and0000(init_reg.quo_reg_1__and00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  678. init_reg.quo_reg_1__and0001(init_reg.quo_reg_1__and00011:O) | NONE(init_reg.quo_reg_1) | 1 |
  679. init_reg.quo_reg_20__and0000(init_reg.quo_reg_20__and00001:O) | NONE(init_reg.quo_reg_20) | 1 |
  680. init_reg.quo_reg_20__and0001(init_reg.quo_reg_20__and00011:O) | NONE(init_reg.quo_reg_20) | 1 |
  681. init_reg.quo_reg_21__and0000(init_reg.quo_reg_21__and00001:O) | NONE(init_reg.quo_reg_21) | 1 |
  682. init_reg.quo_reg_21__and0001(init_reg.quo_reg_21__and00011:O) | NONE(init_reg.quo_reg_21) | 1 |
  683. init_reg.quo_reg_22__and0000(init_reg.quo_reg_22__and00001:O) | NONE(init_reg.quo_reg_22) | 1 |
  684. init_reg.quo_reg_22__and0001(init_reg.quo_reg_22__and00011:O) | NONE(init_reg.quo_reg_22) | 1 |
  685. init_reg.quo_reg_23__and0000(init_reg.quo_reg_23__and00001:O) | NONE(init_reg.quo_reg_23) | 1 |
  686. init_reg.quo_reg_23__and0001(init_reg.quo_reg_23__and00011:O) | NONE(init_reg.quo_reg_23) | 1 |
  687. init_reg.quo_reg_24__and0000(init_reg.quo_reg_24__and00001:O) | NONE(init_reg.quo_reg_24) | 1 |
  688. init_reg.quo_reg_24__and0001(init_reg.quo_reg_24__and00011:O) | NONE(init_reg.quo_reg_24) | 1 |
  689. init_reg.quo_reg_25__and0000(init_reg.quo_reg_25__and00001:O) | NONE(init_reg.quo_reg_25) | 1 |
  690. init_reg.quo_reg_25__and0001(init_reg.quo_reg_25__and00011:O) | NONE(init_reg.quo_reg_25) | 1 |
  691. init_reg.quo_reg_26__and0000(init_reg.quo_reg_26__and00001:O) | NONE(init_reg.quo_reg_26) | 1 |
  692. init_reg.quo_reg_26__and0001(init_reg.quo_reg_26__and00011:O) | NONE(init_reg.quo_reg_26) | 1 |
  693. init_reg.quo_reg_27__and0000(init_reg.quo_reg_27__and00001:O) | NONE(init_reg.quo_reg_27) | 1 |
  694. init_reg.quo_reg_27__and0001(init_reg.quo_reg_27__and00011:O) | NONE(init_reg.quo_reg_27) | 1 |
  695. init_reg.quo_reg_28__and0000(init_reg.quo_reg_28__and00001:O) | NONE(init_reg.quo_reg_28) | 1 |
  696. init_reg.quo_reg_28__and0001(init_reg.quo_reg_28__and00011:O) | NONE(init_reg.quo_reg_28) | 1 |
  697. init_reg.quo_reg_29__and0000(init_reg.quo_reg_29__and00001:O) | NONE(init_reg.quo_reg_29) | 1 |
  698. init_reg.quo_reg_29__and0001(init_reg.quo_reg_29__and00011:O) | NONE(init_reg.quo_reg_29) | 1 |
  699. init_reg.quo_reg_2__and0000(init_reg.quo_reg_2__and00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  700. init_reg.quo_reg_2__and0001(init_reg.quo_reg_2__and00011:O) | NONE(init_reg.quo_reg_2) | 1 |
  701. init_reg.quo_reg_30__and0000(init_reg.quo_reg_30__and00001:O) | NONE(init_reg.quo_reg_30) | 1 |
  702. init_reg.quo_reg_30__and0001(init_reg.quo_reg_30__and00011:O) | NONE(init_reg.quo_reg_30) | 1 |
  703. init_reg.quo_reg_3__and0000(init_reg.quo_reg_3__and00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  704. init_reg.quo_reg_3__and0001(init_reg.quo_reg_3__and00011:O) | NONE(init_reg.quo_reg_3) | 1 |
  705. init_reg.quo_reg_4__and0000(init_reg.quo_reg_4__and00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  706. init_reg.quo_reg_4__and0001(init_reg.quo_reg_4__and00011:O) | NONE(init_reg.quo_reg_4) | 1 |
  707. init_reg.quo_reg_5__and0000(init_reg.quo_reg_5__and00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  708. init_reg.quo_reg_5__and0001(init_reg.quo_reg_5__and00011:O) | NONE(init_reg.quo_reg_5) | 1 |
  709. init_reg.quo_reg_6__and0000(init_reg.quo_reg_6__and00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  710. init_reg.quo_reg_6__and0001(init_reg.quo_reg_6__and00011:O) | NONE(init_reg.quo_reg_6) | 1 |
  711. init_reg.quo_reg_7__and0000(init_reg.quo_reg_7__and00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  712. init_reg.quo_reg_7__and0001(init_reg.quo_reg_7__and00011:O) | NONE(init_reg.quo_reg_7) | 1 |
  713. init_reg.quo_reg_8__and0000(init_reg.quo_reg_8__and00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  714. init_reg.quo_reg_8__and0001(init_reg.quo_reg_8__and00011:O) | NONE(init_reg.quo_reg_8) | 1 |
  715. init_reg.quo_reg_9__and0000(init_reg.quo_reg_9__and00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  716. init_reg.quo_reg_9__and0001(init_reg.quo_reg_9__and00011:O) | NONE(init_reg.quo_reg_9) | 1 |
  717. init_reg.re_reg_0__and0000(init_reg.re_reg_0__and00001:O) | NONE(init_reg.re_reg_0) | 1 |
  718. init_reg.re_reg_0__or0000(init_reg.re_reg_0__or00001:O) | NONE(init_reg.re_reg_0) | 1 |
  719. init_reg.re_reg_10__and0000(init_reg.re_reg_10__and00001:O) | NONE(init_reg.re_reg_10) | 1 |
  720. init_reg.re_reg_10__or0000(init_reg.re_reg_10__or00001:O) | NONE(init_reg.re_reg_10) | 1 |
  721. init_reg.re_reg_11__and0000(init_reg.re_reg_11__and00001:O) | NONE(init_reg.re_reg_11) | 1 |
  722. init_reg.re_reg_11__or0000(init_reg.re_reg_11__or00001:O) | NONE(init_reg.re_reg_11) | 1 |
  723. init_reg.re_reg_12__and0000(init_reg.re_reg_12__and00001:O) | NONE(init_reg.re_reg_12) | 1 |
  724. init_reg.re_reg_12__or0000(init_reg.re_reg_12__or00001:O) | NONE(init_reg.re_reg_12) | 1 |
  725. init_reg.re_reg_13__and0000(init_reg.re_reg_13__and00001:O) | NONE(init_reg.re_reg_13) | 1 |
  726. init_reg.re_reg_13__or0000(init_reg.re_reg_13__or00001:O) | NONE(init_reg.re_reg_13) | 1 |
  727. init_reg.re_reg_14__and0000(init_reg.re_reg_14__and00001:O) | NONE(init_reg.re_reg_14) | 1 |
  728. init_reg.re_reg_14__or0000(init_reg.re_reg_14__or00001:O) | NONE(init_reg.re_reg_14) | 1 |
  729. init_reg.re_reg_15__and0000(init_reg.re_reg_15__and00001:O) | NONE(init_reg.re_reg_15) | 1 |
  730. init_reg.re_reg_15__or0000(init_reg.re_reg_15__or00001:O) | NONE(init_reg.re_reg_15) | 1 |
  731. init_reg.re_reg_16__and0000(init_reg.re_reg_16__and00001:O) | NONE(init_reg.re_reg_16) | 1 |
  732. init_reg.re_reg_16__or0000(init_reg.re_reg_16__or00001:O) | NONE(init_reg.re_reg_16) | 1 |
  733. init_reg.re_reg_17__and0000(init_reg.re_reg_17__and00001:O) | NONE(init_reg.re_reg_17) | 1 |
  734. init_reg.re_reg_17__or0000(init_reg.re_reg_17__or00001:O) | NONE(init_reg.re_reg_17) | 1 |
  735. init_reg.re_reg_18__and0000(init_reg.re_reg_18__and00001:O) | NONE(init_reg.re_reg_18) | 1 |
  736. init_reg.re_reg_18__or0000(init_reg.re_reg_18__or00001:O) | NONE(init_reg.re_reg_18) | 1 |
  737. init_reg.re_reg_19__and0000(init_reg.re_reg_19__and00001:O) | NONE(init_reg.re_reg_19) | 1 |
  738. init_reg.re_reg_19__or0000(init_reg.re_reg_19__or00001:O) | NONE(init_reg.re_reg_19) | 1 |
  739. init_reg.re_reg_1__and0000(init_reg.re_reg_1__and00001:O) | NONE(init_reg.re_reg_1) | 1 |
  740. init_reg.re_reg_1__or0000(init_reg.re_reg_1__or00001:O) | NONE(init_reg.re_reg_1) | 1 |
  741. init_reg.re_reg_20__and0000(init_reg.re_reg_20__and00001:O) | NONE(init_reg.re_reg_20) | 1 |
  742. init_reg.re_reg_20__or0000(init_reg.re_reg_20__or00001:O) | NONE(init_reg.re_reg_20) | 1 |
  743. init_reg.re_reg_21__and0000(init_reg.re_reg_21__and00001:O) | NONE(init_reg.re_reg_21) | 1 |
  744. init_reg.re_reg_21__or0000(init_reg.re_reg_21__or00001:O) | NONE(init_reg.re_reg_21) | 1 |
  745. init_reg.re_reg_22__and0000(init_reg.re_reg_22__and00001:O) | NONE(init_reg.re_reg_22) | 1 |
  746. init_reg.re_reg_22__or0000(init_reg.re_reg_22__or00001:O) | NONE(init_reg.re_reg_22) | 1 |
  747. init_reg.re_reg_23__and0000(init_reg.re_reg_23__and00001:O) | NONE(init_reg.re_reg_23) | 1 |
  748. init_reg.re_reg_23__or0000(init_reg.re_reg_23__or00001:O) | NONE(init_reg.re_reg_23) | 1 |
  749. init_reg.re_reg_24__and0000(init_reg.re_reg_24__and00001:O) | NONE(init_reg.re_reg_24) | 1 |
  750. init_reg.re_reg_24__or0000(init_reg.re_reg_24__or00001:O) | NONE(init_reg.re_reg_24) | 1 |
  751. init_reg.re_reg_25__and0000(init_reg.re_reg_25__and00001:O) | NONE(init_reg.re_reg_25) | 1 |
  752. init_reg.re_reg_25__or0000(init_reg.re_reg_25__or00001:O) | NONE(init_reg.re_reg_25) | 1 |
  753. init_reg.re_reg_26__and0000(init_reg.re_reg_26__and00001:O) | NONE(init_reg.re_reg_26) | 1 |
  754. init_reg.re_reg_26__or0000(init_reg.re_reg_26__or00001:O) | NONE(init_reg.re_reg_26) | 1 |
  755. init_reg.re_reg_27__and0000(init_reg.re_reg_27__and00001:O) | NONE(init_reg.re_reg_27) | 1 |
  756. init_reg.re_reg_27__or0000(init_reg.re_reg_27__or00001:O) | NONE(init_reg.re_reg_27) | 1 |
  757. init_reg.re_reg_28__and0000(init_reg.re_reg_28__and00001:O) | NONE(init_reg.re_reg_28) | 1 |
  758. init_reg.re_reg_28__or0000(init_reg.re_reg_28__or00001:O) | NONE(init_reg.re_reg_28) | 1 |
  759. init_reg.re_reg_29__and0000(init_reg.re_reg_29__and00001:O) | NONE(init_reg.re_reg_29) | 1 |
  760. init_reg.re_reg_29__or0000(init_reg.re_reg_29__or00001:O) | NONE(init_reg.re_reg_29) | 1 |
  761. init_reg.re_reg_2__and0000(init_reg.re_reg_2__and00001:O) | NONE(init_reg.re_reg_2) | 1 |
  762. init_reg.re_reg_2__or0000(init_reg.re_reg_2__or00001:O) | NONE(init_reg.re_reg_2) | 1 |
  763. init_reg.re_reg_30__and0000(init_reg.re_reg_30__and00001:O) | NONE(init_reg.re_reg_30) | 1 |
  764. init_reg.re_reg_30__or0000(init_reg.re_reg_30__or00001:O) | NONE(init_reg.re_reg_30) | 1 |
  765. init_reg.re_reg_3__and0000(init_reg.re_reg_3__and00001:O) | NONE(init_reg.re_reg_3) | 1 |
  766. init_reg.re_reg_3__or0000(init_reg.re_reg_3__or00001:O) | NONE(init_reg.re_reg_3) | 1 |
  767. init_reg.re_reg_4__and0000(init_reg.re_reg_4__and00001:O) | NONE(init_reg.re_reg_4) | 1 |
  768. init_reg.re_reg_4__or0000(init_reg.re_reg_4__or00001:O) | NONE(init_reg.re_reg_4) | 1 |
  769. init_reg.re_reg_5__and0000(init_reg.re_reg_5__and00001:O) | NONE(init_reg.re_reg_5) | 1 |
  770. init_reg.re_reg_5__or0000(init_reg.re_reg_5__or00001:O) | NONE(init_reg.re_reg_5) | 1 |
  771. init_reg.re_reg_6__and0000(init_reg.re_reg_6__and00001:O) | NONE(init_reg.re_reg_6) | 1 |
  772. init_reg.re_reg_6__or0000(init_reg.re_reg_6__or00001:O) | NONE(init_reg.re_reg_6) | 1 |
  773. init_reg.re_reg_7__and0000(init_reg.re_reg_7__and00001:O) | NONE(init_reg.re_reg_7) | 1 |
  774. init_reg.re_reg_7__or0000(init_reg.re_reg_7__or00001:O) | NONE(init_reg.re_reg_7) | 1 |
  775. init_reg.re_reg_8__and0000(init_reg.re_reg_8__and00001:O) | NONE(init_reg.re_reg_8) | 1 |
  776. init_reg.re_reg_8__or0000(init_reg.re_reg_8__or00001:O) | NONE(init_reg.re_reg_8) | 1 |
  777. init_reg.re_reg_9__and0000(init_reg.re_reg_9__and00001:O) | NONE(init_reg.re_reg_9) | 1 |
  778. init_reg.re_reg_9__or0000(init_reg.re_reg_9__or00001:O) | NONE(init_reg.re_reg_9) | 1 |
  779. init_reg.shift_val_0__or0000(init_reg.shift_val_0__or00001:O) | NONE(init_reg.shift_val_0)| 1 |
  780. init_reg.shift_val_0__or0001(init_reg.shift_val_0__or00011:O) | NONE(init_reg.shift_val_0)| 1 |
  781. init_reg.shift_val_1__and0000(init_reg.shift_val_1__and00001:O)| NONE(init_reg.shift_val_1)| 1 |
  782. init_reg.shift_val_1__or0000(init_reg.shift_val_1__or00001:O) | NONE(init_reg.shift_val_1)| 1 |
  783. init_reg.shift_val_2__and0000(init_reg.shift_val_2__and00001:O)| NONE(init_reg.shift_val_2)| 1 |
  784. init_reg.shift_val_2__or0000(init_reg.shift_val_2__or00001:O) | NONE(init_reg.shift_val_2)| 1 |
  785. init_reg.shift_val_3__and0000(init_reg.shift_val_3__and00001:O)| NONE(init_reg.shift_val_3)| 1 |
  786. init_reg.shift_val_3__or0000(init_reg.shift_val_3__or00001:O) | NONE(init_reg.shift_val_3)| 1 |
  787. init_reg.shift_val_4__and0000(init_reg.shift_val_4__and00001:O)| NONE(init_reg.shift_val_4)| 1 |
  788. init_reg.shift_val_4__or0000(init_reg.shift_val_4__or00001:O) | NONE(init_reg.shift_val_4)| 1 |
  789. init_reg_quo_reg_or0001(init_reg_quo_reg_or00011:O) | NONE(init_reg.quo_reg_31) | 1 |
  790. ---------------------------------------------------------------+---------------------------+-------+
  791.  
  792. Timing Summary:
  793. ---------------
  794. Speed Grade: -1
  795.  
  796. Minimum period: 43.445ns (Maximum Frequency: 23.018MHz)
  797. Minimum input arrival time before clock: 40.141ns
  798. Maximum output required time after clock: 3.259ns
  799. Maximum combinational path delay: No path found
  800.  
  801. Timing Detail:
  802. --------------
  803. All values displayed in nanoseconds (ns)
  804.  
  805. =========================================================================
  806. Timing constraint: Default period analysis for Clock 'mclk1'
  807. Clock period: 43.445ns (frequency: 23.018MHz)
  808. Total number of paths / destination ports: 7210344478253649251208749146701824 / 337
  809. -------------------------------------------------------------------------
  810. Delay: 43.445ns (Levels of Logic = 234)
  811. Source: k_reg.re_reg_0 (FF)
  812. Destination: re_0 (FF)
  813. Source Clock: mclk1 rising
  814. Destination Clock: mclk1 rising
  815.  
  816. Data Path: k_reg.re_reg_0 to re_0
  817. Gate Net
  818. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  819. ---------------------------------------- ------------
  820. FDE:C->Q 2 0.471 0.715 k_reg.re_reg_0 (k_reg.re_reg_0)
  821. LUT3:I0->O 1 0.094 0.000 v_reg0_re_reg_mux0000<0>1 (v_reg0_re_reg_mux0000<0>)
  822. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0018_cy<0> (Madd_v_re_addsub0018_cy<0>)
  823. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<1> (Madd_v_re_addsub0018_cy<1>)
  824. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<2> (Madd_v_re_addsub0018_cy<2>)
  825. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<3> (Madd_v_re_addsub0018_cy<3>)
  826. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<4> (Madd_v_re_addsub0018_cy<4>)
  827. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<5> (Madd_v_re_addsub0018_cy<5>)
  828. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<6> (Madd_v_re_addsub0018_cy<6>)
  829. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<7> (Madd_v_re_addsub0018_cy<7>)
  830. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<8> (Madd_v_re_addsub0018_cy<8>)
  831. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<9> (Madd_v_re_addsub0018_cy<9>)
  832. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<10> (Madd_v_re_addsub0018_cy<10>)
  833. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<11> (Madd_v_re_addsub0018_cy<11>)
  834. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<12> (Madd_v_re_addsub0018_cy<12>)
  835. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<13> (Madd_v_re_addsub0018_cy<13>)
  836. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<14> (Madd_v_re_addsub0018_cy<14>)
  837. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<15> (Madd_v_re_addsub0018_cy<15>)
  838. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<16> (Madd_v_re_addsub0018_cy<16>)
  839. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<17> (Madd_v_re_addsub0018_cy<17>)
  840. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<18> (Madd_v_re_addsub0018_cy<18>)
  841. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<19> (Madd_v_re_addsub0018_cy<19>)
  842. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<20> (Madd_v_re_addsub0018_cy<20>)
  843. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<21> (Madd_v_re_addsub0018_cy<21>)
  844. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<22> (Madd_v_re_addsub0018_cy<22>)
  845. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<23> (Madd_v_re_addsub0018_cy<23>)
  846. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<24> (Madd_v_re_addsub0018_cy<24>)
  847. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<25> (Madd_v_re_addsub0018_cy<25>)
  848. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<26> (Madd_v_re_addsub0018_cy<26>)
  849. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<27> (Madd_v_re_addsub0018_cy<27>)
  850. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<28> (Madd_v_re_addsub0018_cy<28>)
  851. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<29> (Madd_v_re_addsub0018_cy<29>)
  852. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<30> (Madd_v_re_addsub0018_cy<30>)
  853. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<31> (Madd_v_re_addsub0018_cy<31>)
  854. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<32> (Madd_v_re_addsub0018_cy<32>)
  855. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0018_cy<33> (Madd_v_re_addsub0018_cy<33>)
  856. XORCY:CI->O 5 0.357 0.502 Madd_v_re_addsub0018_xor<34> (v_re_addsub0018<34>)
  857. LUT6:I5->O 1 0.094 0.789 Sh1301_SW1 (N1786)
  858. LUT6:I2->O 10 0.094 0.529 Sh1301 (Sh130)
  859. LUT6:I5->O 6 0.094 0.507 Sh1541 (Sh154)
  860. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0017_lut<6> (Madd_v_re_addsub0017_lut<6>)
  861. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0017_cy<6> (Madd_v_re_addsub0017_cy<6>)
  862. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<7> (Madd_v_re_addsub0017_cy<7>)
  863. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<8> (Madd_v_re_addsub0017_cy<8>)
  864. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<9> (Madd_v_re_addsub0017_cy<9>)
  865. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<10> (Madd_v_re_addsub0017_cy<10>)
  866. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<11> (Madd_v_re_addsub0017_cy<11>)
  867. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<12> (Madd_v_re_addsub0017_cy<12>)
  868. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<13> (Madd_v_re_addsub0017_cy<13>)
  869. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<14> (Madd_v_re_addsub0017_cy<14>)
  870. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<15> (Madd_v_re_addsub0017_cy<15>)
  871. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<16> (Madd_v_re_addsub0017_cy<16>)
  872. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<17> (Madd_v_re_addsub0017_cy<17>)
  873. XORCY:CI->O 3 0.357 0.491 Madd_v_re_addsub0017_xor<18> (v_re_addsub0017<18>)
  874. LUT4:I3->O 1 0.094 0.000 Madd_v_re_addsub0016_lut<18> (Madd_v_re_addsub0016_lut<18>)
  875. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0016_cy<18> (Madd_v_re_addsub0016_cy<18>)
  876. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0016_cy<19> (Madd_v_re_addsub0016_cy<19>)
  877. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0016_cy<20> (Madd_v_re_addsub0016_cy<20>)
  878. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0016_cy<21> (Madd_v_re_addsub0016_cy<21>)
  879. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0016_cy<22> (Madd_v_re_addsub0016_cy<22>)
  880. XORCY:CI->O 3 0.357 0.491 Madd_v_re_addsub0016_xor<23> (v_re_addsub0016<23>)
  881. LUT5:I4->O 1 0.094 0.000 Madd_v_re_addsub0015_lut<23> (Madd_v_re_addsub0015_lut<23>)
  882. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0015_cy<23> (Madd_v_re_addsub0015_cy<23>)
  883. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0015_xor<24> (v_re_addsub0015<24>)
  884. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0014_lut<24> (Madd_v_re_addsub0014_lut<24>)
  885. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0014_cy<24> (Madd_v_re_addsub0014_cy<24>)
  886. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0014_xor<25> (v_re_addsub0014<25>)
  887. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0012_lut<25> (Madd_v_re_addsub0012_lut<25>)
  888. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0012_cy<25> (Madd_v_re_addsub0012_cy<25>)
  889. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0012_xor<26> (v_re_addsub0012<26>)
  890. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0011_lut<26> (Madd_v_re_addsub0011_lut<26>)
  891. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0011_cy<26> (Madd_v_re_addsub0011_cy<26>)
  892. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0011_xor<27> (v_re_addsub0011<27>)
  893. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0009_lut<27> (Madd_v_re_addsub0009_lut<27>)
  894. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0009_cy<27> (Madd_v_re_addsub0009_cy<27>)
  895. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0009_xor<28> (v_re_addsub0009<28>)
  896. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0007_lut<28> (Madd_v_re_addsub0007_lut<28>)
  897. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0007_cy<28> (Madd_v_re_addsub0007_cy<28>)
  898. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0007_xor<29> (v_re_addsub0007<29>)
  899. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0005_lut<29> (Madd_v_re_addsub0005_lut<29>)
  900. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0005_cy<29> (Madd_v_re_addsub0005_cy<29>)
  901. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0005_xor<30> (v_re_addsub0005<30>)
  902. LUT6:I5->O 6 0.094 1.000 v_re_mux0009<30>1 (v_re_mux0009<30>)
  903. LUT5:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0008_lut<15> (Mcompar_v_re_cmp_ge0008_lut<15>)
  904. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0008_cy<15> (Mcompar_v_re_cmp_ge0008_cy<15>)
  905. MUXCY:CI->O 334 0.254 0.663 Mcompar_v_re_cmp_ge0008_cy<16> (v_re_cmp_ge0008)
  906. LUT3:I2->O 2 0.094 0.794 v_re_mux0010<0>1 (v_re_mux0010<0>)
  907. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0007_lut<0> (Mcompar_v_re_cmp_ge0007_lut<0>)
  908. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0007_cy<0> (Mcompar_v_re_cmp_ge0007_cy<0>)
  909. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<1> (Mcompar_v_re_cmp_ge0007_cy<1>)
  910. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<2> (Mcompar_v_re_cmp_ge0007_cy<2>)
  911. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<3> (Mcompar_v_re_cmp_ge0007_cy<3>)
  912. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<4> (Mcompar_v_re_cmp_ge0007_cy<4>)
  913. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<5> (Mcompar_v_re_cmp_ge0007_cy<5>)
  914. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<6> (Mcompar_v_re_cmp_ge0007_cy<6>)
  915. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<7> (Mcompar_v_re_cmp_ge0007_cy<7>)
  916. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<8> (Mcompar_v_re_cmp_ge0007_cy<8>)
  917. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<9> (Mcompar_v_re_cmp_ge0007_cy<9>)
  918. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<10> (Mcompar_v_re_cmp_ge0007_cy<10>)
  919. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<11> (Mcompar_v_re_cmp_ge0007_cy<11>)
  920. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<12> (Mcompar_v_re_cmp_ge0007_cy<12>)
  921. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<13> (Mcompar_v_re_cmp_ge0007_cy<13>)
  922. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<14> (Mcompar_v_re_cmp_ge0007_cy<14>)
  923. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<15> (Mcompar_v_re_cmp_ge0007_cy<15>)
  924. MUXCY:CI->O 179 0.254 0.635 Mcompar_v_re_cmp_ge0007_cy<16> (v_re_cmp_ge0007)
  925. LUT5:I4->O 6 0.094 0.816 v_re_mux0011<0>1 (v_re_mux0011<0>)
  926. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0006_lut<0> (Mcompar_v_re_cmp_ge0006_lut<0>)
  927. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0006_cy<0> (Mcompar_v_re_cmp_ge0006_cy<0>)
  928. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<1> (Mcompar_v_re_cmp_ge0006_cy<1>)
  929. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<2> (Mcompar_v_re_cmp_ge0006_cy<2>)
  930. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<3> (Mcompar_v_re_cmp_ge0006_cy<3>)
  931. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<4> (Mcompar_v_re_cmp_ge0006_cy<4>)
  932. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<5> (Mcompar_v_re_cmp_ge0006_cy<5>)
  933. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<6> (Mcompar_v_re_cmp_ge0006_cy<6>)
  934. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<7> (Mcompar_v_re_cmp_ge0006_cy<7>)
  935. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<8> (Mcompar_v_re_cmp_ge0006_cy<8>)
  936. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<9> (Mcompar_v_re_cmp_ge0006_cy<9>)
  937. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<10> (Mcompar_v_re_cmp_ge0006_cy<10>)
  938. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<11> (Mcompar_v_re_cmp_ge0006_cy<11>)
  939. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<12> (Mcompar_v_re_cmp_ge0006_cy<12>)
  940. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<13> (Mcompar_v_re_cmp_ge0006_cy<13>)
  941. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<14> (Mcompar_v_re_cmp_ge0006_cy<14>)
  942. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<15> (Mcompar_v_re_cmp_ge0006_cy<15>)
  943. MUXCY:CI->O 214 0.254 0.641 Mcompar_v_re_cmp_ge0006_cy<16> (v_re_cmp_ge0006)
  944. LUT3:I2->O 2 0.094 0.794 v_re_mux0012<0>1 (v_re_mux0012<0>)
  945. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0005_lut<0> (Mcompar_v_re_cmp_ge0005_lut<0>)
  946. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0005_cy<0> (Mcompar_v_re_cmp_ge0005_cy<0>)
  947. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<1> (Mcompar_v_re_cmp_ge0005_cy<1>)
  948. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<2> (Mcompar_v_re_cmp_ge0005_cy<2>)
  949. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<3> (Mcompar_v_re_cmp_ge0005_cy<3>)
  950. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<4> (Mcompar_v_re_cmp_ge0005_cy<4>)
  951. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<5> (Mcompar_v_re_cmp_ge0005_cy<5>)
  952. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<6> (Mcompar_v_re_cmp_ge0005_cy<6>)
  953. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<7> (Mcompar_v_re_cmp_ge0005_cy<7>)
  954. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<8> (Mcompar_v_re_cmp_ge0005_cy<8>)
  955. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<9> (Mcompar_v_re_cmp_ge0005_cy<9>)
  956. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<10> (Mcompar_v_re_cmp_ge0005_cy<10>)
  957. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<11> (Mcompar_v_re_cmp_ge0005_cy<11>)
  958. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<12> (Mcompar_v_re_cmp_ge0005_cy<12>)
  959. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<13> (Mcompar_v_re_cmp_ge0005_cy<13>)
  960. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<14> (Mcompar_v_re_cmp_ge0005_cy<14>)
  961. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<15> (Mcompar_v_re_cmp_ge0005_cy<15>)
  962. MUXCY:CI->O 151 0.254 0.629 Mcompar_v_re_cmp_ge0005_cy<16> (v_re_cmp_ge0005)
  963. LUT5:I4->O 6 0.094 0.816 v_re_mux0013<0>1 (v_re_mux0013<0>)
  964. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0004_lut<0> (Mcompar_v_re_cmp_ge0004_lut<0>)
  965. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0004_cy<0> (Mcompar_v_re_cmp_ge0004_cy<0>)
  966. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<1> (Mcompar_v_re_cmp_ge0004_cy<1>)
  967. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<2> (Mcompar_v_re_cmp_ge0004_cy<2>)
  968. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<3> (Mcompar_v_re_cmp_ge0004_cy<3>)
  969. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<4> (Mcompar_v_re_cmp_ge0004_cy<4>)
  970. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<5> (Mcompar_v_re_cmp_ge0004_cy<5>)
  971. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<6> (Mcompar_v_re_cmp_ge0004_cy<6>)
  972. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<7> (Mcompar_v_re_cmp_ge0004_cy<7>)
  973. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<8> (Mcompar_v_re_cmp_ge0004_cy<8>)
  974. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<9> (Mcompar_v_re_cmp_ge0004_cy<9>)
  975. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<10> (Mcompar_v_re_cmp_ge0004_cy<10>)
  976. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<11> (Mcompar_v_re_cmp_ge0004_cy<11>)
  977. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<12> (Mcompar_v_re_cmp_ge0004_cy<12>)
  978. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<13> (Mcompar_v_re_cmp_ge0004_cy<13>)
  979. MUXCY:CI->O 1 0.254 0.480 Mcompar_v_re_cmp_ge0004_cy<14> (Mcompar_v_re_cmp_ge0004_cy<14>)
  980. LUT5:I4->O 267 0.094 0.651 Mcompar_v_re_cmp_ge0004_cy<16>1 (v_re_cmp_ge0004)
  981. LUT3:I2->O 2 0.094 0.794 v_re_mux0014<0>1 (v_re_mux0014<0>)
  982. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0003_lut<0> (Mcompar_v_re_cmp_ge0003_lut<0>)
  983. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0003_cy<0> (Mcompar_v_re_cmp_ge0003_cy<0>)
  984. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<1> (Mcompar_v_re_cmp_ge0003_cy<1>)
  985. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<2> (Mcompar_v_re_cmp_ge0003_cy<2>)
  986. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<3> (Mcompar_v_re_cmp_ge0003_cy<3>)
  987. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<4> (Mcompar_v_re_cmp_ge0003_cy<4>)
  988. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<5> (Mcompar_v_re_cmp_ge0003_cy<5>)
  989. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<6> (Mcompar_v_re_cmp_ge0003_cy<6>)
  990. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<7> (Mcompar_v_re_cmp_ge0003_cy<7>)
  991. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<8> (Mcompar_v_re_cmp_ge0003_cy<8>)
  992. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<9> (Mcompar_v_re_cmp_ge0003_cy<9>)
  993. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<10> (Mcompar_v_re_cmp_ge0003_cy<10>)
  994. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<11> (Mcompar_v_re_cmp_ge0003_cy<11>)
  995. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<12> (Mcompar_v_re_cmp_ge0003_cy<12>)
  996. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<13> (Mcompar_v_re_cmp_ge0003_cy<13>)
  997. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<14> (Mcompar_v_re_cmp_ge0003_cy<14>)
  998. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<15> (Mcompar_v_re_cmp_ge0003_cy<15>)
  999. MUXCY:CI->O 176 0.254 0.634 Mcompar_v_re_cmp_ge0003_cy<16> (v_re_cmp_ge0003)
  1000. LUT5:I4->O 6 0.094 0.816 v_re_mux0015<0>1 (v_re_mux0015<0>)
  1001. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0002_lut<0> (Mcompar_v_re_cmp_ge0002_lut<0>)
  1002. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0002_cy<0> (Mcompar_v_re_cmp_ge0002_cy<0>)
  1003. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<1> (Mcompar_v_re_cmp_ge0002_cy<1>)
  1004. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<2> (Mcompar_v_re_cmp_ge0002_cy<2>)
  1005. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<3> (Mcompar_v_re_cmp_ge0002_cy<3>)
  1006. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<4> (Mcompar_v_re_cmp_ge0002_cy<4>)
  1007. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<5> (Mcompar_v_re_cmp_ge0002_cy<5>)
  1008. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<6> (Mcompar_v_re_cmp_ge0002_cy<6>)
  1009. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<7> (Mcompar_v_re_cmp_ge0002_cy<7>)
  1010. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<8> (Mcompar_v_re_cmp_ge0002_cy<8>)
  1011. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<9> (Mcompar_v_re_cmp_ge0002_cy<9>)
  1012. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<10> (Mcompar_v_re_cmp_ge0002_cy<10>)
  1013. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<11> (Mcompar_v_re_cmp_ge0002_cy<11>)
  1014. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<12> (Mcompar_v_re_cmp_ge0002_cy<12>)
  1015. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<13> (Mcompar_v_re_cmp_ge0002_cy<13>)
  1016. MUXCY:CI->O 1 0.254 0.480 Mcompar_v_re_cmp_ge0002_cy<14> (Mcompar_v_re_cmp_ge0002_cy<14>)
  1017. LUT5:I4->O 236 0.094 0.645 Mcompar_v_re_cmp_ge0002_cy<16>1 (v_re_cmp_ge0002)
  1018. LUT3:I2->O 3 0.094 0.800 v_re_mux0016<0>1 (v_re_mux0016<0>)
  1019. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0001_lut<0> (Mcompar_v_re_cmp_ge0001_lut<0>)
  1020. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0001_cy<0> (Mcompar_v_re_cmp_ge0001_cy<0>)
  1021. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<1> (Mcompar_v_re_cmp_ge0001_cy<1>)
  1022. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<2> (Mcompar_v_re_cmp_ge0001_cy<2>)
  1023. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<3> (Mcompar_v_re_cmp_ge0001_cy<3>)
  1024. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<4> (Mcompar_v_re_cmp_ge0001_cy<4>)
  1025. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<5> (Mcompar_v_re_cmp_ge0001_cy<5>)
  1026. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<6> (Mcompar_v_re_cmp_ge0001_cy<6>)
  1027. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<7> (Mcompar_v_re_cmp_ge0001_cy<7>)
  1028. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<8> (Mcompar_v_re_cmp_ge0001_cy<8>)
  1029. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<9> (Mcompar_v_re_cmp_ge0001_cy<9>)
  1030. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<10> (Mcompar_v_re_cmp_ge0001_cy<10>)
  1031. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<11> (Mcompar_v_re_cmp_ge0001_cy<11>)
  1032. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<12> (Mcompar_v_re_cmp_ge0001_cy<12>)
  1033. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<13> (Mcompar_v_re_cmp_ge0001_cy<13>)
  1034. MUXCY:CI->O 1 0.254 0.480 Mcompar_v_re_cmp_ge0001_cy<14> (Mcompar_v_re_cmp_ge0001_cy<14>)
  1035. LUT5:I4->O 164 0.094 0.632 Mcompar_v_re_cmp_ge0001_cy<16>1 (v_re_cmp_ge0001)
  1036. LUT5:I4->O 2 0.094 0.794 v_re_mux0017<0>1 (v_re_mux0017<0>)
  1037. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0000_lut<0> (Mcompar_v_re_cmp_ge0000_lut<0>)
  1038. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0000_cy<0> (Mcompar_v_re_cmp_ge0000_cy<0>)
  1039. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<1> (Mcompar_v_re_cmp_ge0000_cy<1>)
  1040. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<2> (Mcompar_v_re_cmp_ge0000_cy<2>)
  1041. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<3> (Mcompar_v_re_cmp_ge0000_cy<3>)
  1042. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<4> (Mcompar_v_re_cmp_ge0000_cy<4>)
  1043. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<5> (Mcompar_v_re_cmp_ge0000_cy<5>)
  1044. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<6> (Mcompar_v_re_cmp_ge0000_cy<6>)
  1045. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<7> (Mcompar_v_re_cmp_ge0000_cy<7>)
  1046. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<8> (Mcompar_v_re_cmp_ge0000_cy<8>)
  1047. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<9> (Mcompar_v_re_cmp_ge0000_cy<9>)
  1048. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<10> (Mcompar_v_re_cmp_ge0000_cy<10>)
  1049. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<11> (Mcompar_v_re_cmp_ge0000_cy<11>)
  1050. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<12> (Mcompar_v_re_cmp_ge0000_cy<12>)
  1051. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<13> (Mcompar_v_re_cmp_ge0000_cy<13>)
  1052. MUXCY:CI->O 1 0.254 0.480 Mcompar_v_re_cmp_ge0000_cy<14> (Mcompar_v_re_cmp_ge0000_cy<14>)
  1053. LUT5:I4->O 64 0.094 0.613 Mcompar_v_re_cmp_ge0000_cy<16>1 (v_re_cmp_ge0000)
  1054. LUT5:I4->O 1 0.094 0.000 v_re_mux0018<31>1 (v_re_mux0018<31>)
  1055. FD:D -0.018 re_31
  1056. ----------------------------------------
  1057. Total 43.445ns (20.939ns logic, 22.506ns route)
  1058. (48.2% logic, 51.8% route)
  1059.  
  1060. =========================================================================
  1061. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  1062. Total number of paths / destination ports: 6960865974154052365649084153856 / 71
  1063. -------------------------------------------------------------------------
  1064. Offset: 40.141ns (Levels of Logic = 202)
  1065. Source: divisor<0> (PAD)
  1066. Destination: re_0 (FF)
  1067. Destination Clock: mclk1 rising
  1068.  
  1069. Data Path: divisor<0> to re_0
  1070. Gate Net
  1071. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1072. ---------------------------------------- ------------
  1073. IBUF:I->O 39 0.818 1.198 divisor_0_IBUF (divisor_0_IBUF1)
  1074. LUT6:I0->O 1 0.094 0.000 Madd_v_re_addsub0017_lut<0> (Madd_v_re_addsub0017_lut<0>)
  1075. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0017_cy<0> (Madd_v_re_addsub0017_cy<0>)
  1076. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<1> (Madd_v_re_addsub0017_cy<1>)
  1077. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<2> (Madd_v_re_addsub0017_cy<2>)
  1078. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<3> (Madd_v_re_addsub0017_cy<3>)
  1079. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<4> (Madd_v_re_addsub0017_cy<4>)
  1080. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<5> (Madd_v_re_addsub0017_cy<5>)
  1081. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<6> (Madd_v_re_addsub0017_cy<6>)
  1082. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<7> (Madd_v_re_addsub0017_cy<7>)
  1083. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<8> (Madd_v_re_addsub0017_cy<8>)
  1084. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<9> (Madd_v_re_addsub0017_cy<9>)
  1085. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<10> (Madd_v_re_addsub0017_cy<10>)
  1086. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<11> (Madd_v_re_addsub0017_cy<11>)
  1087. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<12> (Madd_v_re_addsub0017_cy<12>)
  1088. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<13> (Madd_v_re_addsub0017_cy<13>)
  1089. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<14> (Madd_v_re_addsub0017_cy<14>)
  1090. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<15> (Madd_v_re_addsub0017_cy<15>)
  1091. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<16> (Madd_v_re_addsub0017_cy<16>)
  1092. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0017_cy<17> (Madd_v_re_addsub0017_cy<17>)
  1093. XORCY:CI->O 3 0.357 0.491 Madd_v_re_addsub0017_xor<18> (v_re_addsub0017<18>)
  1094. LUT4:I3->O 1 0.094 0.000 Madd_v_re_addsub0016_lut<18> (Madd_v_re_addsub0016_lut<18>)
  1095. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0016_cy<18> (Madd_v_re_addsub0016_cy<18>)
  1096. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0016_cy<19> (Madd_v_re_addsub0016_cy<19>)
  1097. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0016_cy<20> (Madd_v_re_addsub0016_cy<20>)
  1098. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0016_cy<21> (Madd_v_re_addsub0016_cy<21>)
  1099. MUXCY:CI->O 1 0.026 0.000 Madd_v_re_addsub0016_cy<22> (Madd_v_re_addsub0016_cy<22>)
  1100. XORCY:CI->O 3 0.357 0.491 Madd_v_re_addsub0016_xor<23> (v_re_addsub0016<23>)
  1101. LUT5:I4->O 1 0.094 0.000 Madd_v_re_addsub0015_lut<23> (Madd_v_re_addsub0015_lut<23>)
  1102. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0015_cy<23> (Madd_v_re_addsub0015_cy<23>)
  1103. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0015_xor<24> (v_re_addsub0015<24>)
  1104. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0014_lut<24> (Madd_v_re_addsub0014_lut<24>)
  1105. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0014_cy<24> (Madd_v_re_addsub0014_cy<24>)
  1106. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0014_xor<25> (v_re_addsub0014<25>)
  1107. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0012_lut<25> (Madd_v_re_addsub0012_lut<25>)
  1108. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0012_cy<25> (Madd_v_re_addsub0012_cy<25>)
  1109. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0012_xor<26> (v_re_addsub0012<26>)
  1110. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0011_lut<26> (Madd_v_re_addsub0011_lut<26>)
  1111. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0011_cy<26> (Madd_v_re_addsub0011_cy<26>)
  1112. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0011_xor<27> (v_re_addsub0011<27>)
  1113. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0009_lut<27> (Madd_v_re_addsub0009_lut<27>)
  1114. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0009_cy<27> (Madd_v_re_addsub0009_cy<27>)
  1115. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0009_xor<28> (v_re_addsub0009<28>)
  1116. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0007_lut<28> (Madd_v_re_addsub0007_lut<28>)
  1117. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0007_cy<28> (Madd_v_re_addsub0007_cy<28>)
  1118. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0007_xor<29> (v_re_addsub0007<29>)
  1119. LUT6:I5->O 1 0.094 0.000 Madd_v_re_addsub0005_lut<29> (Madd_v_re_addsub0005_lut<29>)
  1120. MUXCY:S->O 1 0.372 0.000 Madd_v_re_addsub0005_cy<29> (Madd_v_re_addsub0005_cy<29>)
  1121. XORCY:CI->O 2 0.357 0.485 Madd_v_re_addsub0005_xor<30> (v_re_addsub0005<30>)
  1122. LUT6:I5->O 6 0.094 1.000 v_re_mux0009<30>1 (v_re_mux0009<30>)
  1123. LUT5:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0008_lut<15> (Mcompar_v_re_cmp_ge0008_lut<15>)
  1124. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0008_cy<15> (Mcompar_v_re_cmp_ge0008_cy<15>)
  1125. MUXCY:CI->O 334 0.254 0.663 Mcompar_v_re_cmp_ge0008_cy<16> (v_re_cmp_ge0008)
  1126. LUT3:I2->O 2 0.094 0.794 v_re_mux0010<0>1 (v_re_mux0010<0>)
  1127. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0007_lut<0> (Mcompar_v_re_cmp_ge0007_lut<0>)
  1128. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0007_cy<0> (Mcompar_v_re_cmp_ge0007_cy<0>)
  1129. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<1> (Mcompar_v_re_cmp_ge0007_cy<1>)
  1130. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<2> (Mcompar_v_re_cmp_ge0007_cy<2>)
  1131. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<3> (Mcompar_v_re_cmp_ge0007_cy<3>)
  1132. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<4> (Mcompar_v_re_cmp_ge0007_cy<4>)
  1133. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<5> (Mcompar_v_re_cmp_ge0007_cy<5>)
  1134. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<6> (Mcompar_v_re_cmp_ge0007_cy<6>)
  1135. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<7> (Mcompar_v_re_cmp_ge0007_cy<7>)
  1136. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<8> (Mcompar_v_re_cmp_ge0007_cy<8>)
  1137. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<9> (Mcompar_v_re_cmp_ge0007_cy<9>)
  1138. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<10> (Mcompar_v_re_cmp_ge0007_cy<10>)
  1139. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<11> (Mcompar_v_re_cmp_ge0007_cy<11>)
  1140. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<12> (Mcompar_v_re_cmp_ge0007_cy<12>)
  1141. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<13> (Mcompar_v_re_cmp_ge0007_cy<13>)
  1142. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<14> (Mcompar_v_re_cmp_ge0007_cy<14>)
  1143. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0007_cy<15> (Mcompar_v_re_cmp_ge0007_cy<15>)
  1144. MUXCY:CI->O 179 0.254 0.635 Mcompar_v_re_cmp_ge0007_cy<16> (v_re_cmp_ge0007)
  1145. LUT5:I4->O 6 0.094 0.816 v_re_mux0011<0>1 (v_re_mux0011<0>)
  1146. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0006_lut<0> (Mcompar_v_re_cmp_ge0006_lut<0>)
  1147. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0006_cy<0> (Mcompar_v_re_cmp_ge0006_cy<0>)
  1148. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<1> (Mcompar_v_re_cmp_ge0006_cy<1>)
  1149. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<2> (Mcompar_v_re_cmp_ge0006_cy<2>)
  1150. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<3> (Mcompar_v_re_cmp_ge0006_cy<3>)
  1151. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<4> (Mcompar_v_re_cmp_ge0006_cy<4>)
  1152. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<5> (Mcompar_v_re_cmp_ge0006_cy<5>)
  1153. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<6> (Mcompar_v_re_cmp_ge0006_cy<6>)
  1154. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<7> (Mcompar_v_re_cmp_ge0006_cy<7>)
  1155. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<8> (Mcompar_v_re_cmp_ge0006_cy<8>)
  1156. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<9> (Mcompar_v_re_cmp_ge0006_cy<9>)
  1157. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<10> (Mcompar_v_re_cmp_ge0006_cy<10>)
  1158. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<11> (Mcompar_v_re_cmp_ge0006_cy<11>)
  1159. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<12> (Mcompar_v_re_cmp_ge0006_cy<12>)
  1160. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<13> (Mcompar_v_re_cmp_ge0006_cy<13>)
  1161. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<14> (Mcompar_v_re_cmp_ge0006_cy<14>)
  1162. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0006_cy<15> (Mcompar_v_re_cmp_ge0006_cy<15>)
  1163. MUXCY:CI->O 214 0.254 0.641 Mcompar_v_re_cmp_ge0006_cy<16> (v_re_cmp_ge0006)
  1164. LUT3:I2->O 2 0.094 0.794 v_re_mux0012<0>1 (v_re_mux0012<0>)
  1165. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0005_lut<0> (Mcompar_v_re_cmp_ge0005_lut<0>)
  1166. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0005_cy<0> (Mcompar_v_re_cmp_ge0005_cy<0>)
  1167. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<1> (Mcompar_v_re_cmp_ge0005_cy<1>)
  1168. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<2> (Mcompar_v_re_cmp_ge0005_cy<2>)
  1169. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<3> (Mcompar_v_re_cmp_ge0005_cy<3>)
  1170. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<4> (Mcompar_v_re_cmp_ge0005_cy<4>)
  1171. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<5> (Mcompar_v_re_cmp_ge0005_cy<5>)
  1172. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<6> (Mcompar_v_re_cmp_ge0005_cy<6>)
  1173. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<7> (Mcompar_v_re_cmp_ge0005_cy<7>)
  1174. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<8> (Mcompar_v_re_cmp_ge0005_cy<8>)
  1175. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<9> (Mcompar_v_re_cmp_ge0005_cy<9>)
  1176. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<10> (Mcompar_v_re_cmp_ge0005_cy<10>)
  1177. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<11> (Mcompar_v_re_cmp_ge0005_cy<11>)
  1178. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<12> (Mcompar_v_re_cmp_ge0005_cy<12>)
  1179. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<13> (Mcompar_v_re_cmp_ge0005_cy<13>)
  1180. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<14> (Mcompar_v_re_cmp_ge0005_cy<14>)
  1181. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0005_cy<15> (Mcompar_v_re_cmp_ge0005_cy<15>)
  1182. MUXCY:CI->O 151 0.254 0.629 Mcompar_v_re_cmp_ge0005_cy<16> (v_re_cmp_ge0005)
  1183. LUT5:I4->O 6 0.094 0.816 v_re_mux0013<0>1 (v_re_mux0013<0>)
  1184. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0004_lut<0> (Mcompar_v_re_cmp_ge0004_lut<0>)
  1185. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0004_cy<0> (Mcompar_v_re_cmp_ge0004_cy<0>)
  1186. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<1> (Mcompar_v_re_cmp_ge0004_cy<1>)
  1187. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<2> (Mcompar_v_re_cmp_ge0004_cy<2>)
  1188. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<3> (Mcompar_v_re_cmp_ge0004_cy<3>)
  1189. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<4> (Mcompar_v_re_cmp_ge0004_cy<4>)
  1190. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<5> (Mcompar_v_re_cmp_ge0004_cy<5>)
  1191. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<6> (Mcompar_v_re_cmp_ge0004_cy<6>)
  1192. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<7> (Mcompar_v_re_cmp_ge0004_cy<7>)
  1193. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<8> (Mcompar_v_re_cmp_ge0004_cy<8>)
  1194. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<9> (Mcompar_v_re_cmp_ge0004_cy<9>)
  1195. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<10> (Mcompar_v_re_cmp_ge0004_cy<10>)
  1196. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<11> (Mcompar_v_re_cmp_ge0004_cy<11>)
  1197. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<12> (Mcompar_v_re_cmp_ge0004_cy<12>)
  1198. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0004_cy<13> (Mcompar_v_re_cmp_ge0004_cy<13>)
  1199. MUXCY:CI->O 1 0.254 0.480 Mcompar_v_re_cmp_ge0004_cy<14> (Mcompar_v_re_cmp_ge0004_cy<14>)
  1200. LUT5:I4->O 267 0.094 0.651 Mcompar_v_re_cmp_ge0004_cy<16>1 (v_re_cmp_ge0004)
  1201. LUT3:I2->O 2 0.094 0.794 v_re_mux0014<0>1 (v_re_mux0014<0>)
  1202. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0003_lut<0> (Mcompar_v_re_cmp_ge0003_lut<0>)
  1203. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0003_cy<0> (Mcompar_v_re_cmp_ge0003_cy<0>)
  1204. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<1> (Mcompar_v_re_cmp_ge0003_cy<1>)
  1205. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<2> (Mcompar_v_re_cmp_ge0003_cy<2>)
  1206. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<3> (Mcompar_v_re_cmp_ge0003_cy<3>)
  1207. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<4> (Mcompar_v_re_cmp_ge0003_cy<4>)
  1208. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<5> (Mcompar_v_re_cmp_ge0003_cy<5>)
  1209. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<6> (Mcompar_v_re_cmp_ge0003_cy<6>)
  1210. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<7> (Mcompar_v_re_cmp_ge0003_cy<7>)
  1211. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<8> (Mcompar_v_re_cmp_ge0003_cy<8>)
  1212. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<9> (Mcompar_v_re_cmp_ge0003_cy<9>)
  1213. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<10> (Mcompar_v_re_cmp_ge0003_cy<10>)
  1214. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<11> (Mcompar_v_re_cmp_ge0003_cy<11>)
  1215. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<12> (Mcompar_v_re_cmp_ge0003_cy<12>)
  1216. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<13> (Mcompar_v_re_cmp_ge0003_cy<13>)
  1217. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<14> (Mcompar_v_re_cmp_ge0003_cy<14>)
  1218. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0003_cy<15> (Mcompar_v_re_cmp_ge0003_cy<15>)
  1219. MUXCY:CI->O 176 0.254 0.634 Mcompar_v_re_cmp_ge0003_cy<16> (v_re_cmp_ge0003)
  1220. LUT5:I4->O 6 0.094 0.816 v_re_mux0015<0>1 (v_re_mux0015<0>)
  1221. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0002_lut<0> (Mcompar_v_re_cmp_ge0002_lut<0>)
  1222. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0002_cy<0> (Mcompar_v_re_cmp_ge0002_cy<0>)
  1223. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<1> (Mcompar_v_re_cmp_ge0002_cy<1>)
  1224. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<2> (Mcompar_v_re_cmp_ge0002_cy<2>)
  1225. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<3> (Mcompar_v_re_cmp_ge0002_cy<3>)
  1226. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<4> (Mcompar_v_re_cmp_ge0002_cy<4>)
  1227. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<5> (Mcompar_v_re_cmp_ge0002_cy<5>)
  1228. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<6> (Mcompar_v_re_cmp_ge0002_cy<6>)
  1229. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<7> (Mcompar_v_re_cmp_ge0002_cy<7>)
  1230. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<8> (Mcompar_v_re_cmp_ge0002_cy<8>)
  1231. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<9> (Mcompar_v_re_cmp_ge0002_cy<9>)
  1232. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<10> (Mcompar_v_re_cmp_ge0002_cy<10>)
  1233. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<11> (Mcompar_v_re_cmp_ge0002_cy<11>)
  1234. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<12> (Mcompar_v_re_cmp_ge0002_cy<12>)
  1235. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0002_cy<13> (Mcompar_v_re_cmp_ge0002_cy<13>)
  1236. MUXCY:CI->O 1 0.254 0.480 Mcompar_v_re_cmp_ge0002_cy<14> (Mcompar_v_re_cmp_ge0002_cy<14>)
  1237. LUT5:I4->O 236 0.094 0.645 Mcompar_v_re_cmp_ge0002_cy<16>1 (v_re_cmp_ge0002)
  1238. LUT3:I2->O 3 0.094 0.800 v_re_mux0016<0>1 (v_re_mux0016<0>)
  1239. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0001_lut<0> (Mcompar_v_re_cmp_ge0001_lut<0>)
  1240. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0001_cy<0> (Mcompar_v_re_cmp_ge0001_cy<0>)
  1241. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<1> (Mcompar_v_re_cmp_ge0001_cy<1>)
  1242. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<2> (Mcompar_v_re_cmp_ge0001_cy<2>)
  1243. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<3> (Mcompar_v_re_cmp_ge0001_cy<3>)
  1244. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<4> (Mcompar_v_re_cmp_ge0001_cy<4>)
  1245. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<5> (Mcompar_v_re_cmp_ge0001_cy<5>)
  1246. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<6> (Mcompar_v_re_cmp_ge0001_cy<6>)
  1247. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<7> (Mcompar_v_re_cmp_ge0001_cy<7>)
  1248. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<8> (Mcompar_v_re_cmp_ge0001_cy<8>)
  1249. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<9> (Mcompar_v_re_cmp_ge0001_cy<9>)
  1250. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<10> (Mcompar_v_re_cmp_ge0001_cy<10>)
  1251. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<11> (Mcompar_v_re_cmp_ge0001_cy<11>)
  1252. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<12> (Mcompar_v_re_cmp_ge0001_cy<12>)
  1253. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0001_cy<13> (Mcompar_v_re_cmp_ge0001_cy<13>)
  1254. MUXCY:CI->O 1 0.254 0.480 Mcompar_v_re_cmp_ge0001_cy<14> (Mcompar_v_re_cmp_ge0001_cy<14>)
  1255. LUT5:I4->O 164 0.094 0.632 Mcompar_v_re_cmp_ge0001_cy<16>1 (v_re_cmp_ge0001)
  1256. LUT5:I4->O 2 0.094 0.794 v_re_mux0017<0>1 (v_re_mux0017<0>)
  1257. LUT4:I0->O 1 0.094 0.000 Mcompar_v_re_cmp_ge0000_lut<0> (Mcompar_v_re_cmp_ge0000_lut<0>)
  1258. MUXCY:S->O 1 0.372 0.000 Mcompar_v_re_cmp_ge0000_cy<0> (Mcompar_v_re_cmp_ge0000_cy<0>)
  1259. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<1> (Mcompar_v_re_cmp_ge0000_cy<1>)
  1260. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<2> (Mcompar_v_re_cmp_ge0000_cy<2>)
  1261. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<3> (Mcompar_v_re_cmp_ge0000_cy<3>)
  1262. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<4> (Mcompar_v_re_cmp_ge0000_cy<4>)
  1263. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<5> (Mcompar_v_re_cmp_ge0000_cy<5>)
  1264. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<6> (Mcompar_v_re_cmp_ge0000_cy<6>)
  1265. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<7> (Mcompar_v_re_cmp_ge0000_cy<7>)
  1266. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<8> (Mcompar_v_re_cmp_ge0000_cy<8>)
  1267. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<9> (Mcompar_v_re_cmp_ge0000_cy<9>)
  1268. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<10> (Mcompar_v_re_cmp_ge0000_cy<10>)
  1269. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<11> (Mcompar_v_re_cmp_ge0000_cy<11>)
  1270. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<12> (Mcompar_v_re_cmp_ge0000_cy<12>)
  1271. MUXCY:CI->O 1 0.026 0.000 Mcompar_v_re_cmp_ge0000_cy<13> (Mcompar_v_re_cmp_ge0000_cy<13>)
  1272. MUXCY:CI->O 1 0.254 0.480 Mcompar_v_re_cmp_ge0000_cy<14> (Mcompar_v_re_cmp_ge0000_cy<14>)
  1273. LUT5:I4->O 64 0.094 0.613 Mcompar_v_re_cmp_ge0000_cy<16>1 (v_re_cmp_ge0000)
  1274. LUT5:I4->O 1 0.094 0.000 v_re_mux0018<31>1 (v_re_mux0018<31>)
  1275. FD:D -0.018 re_31
  1276. ----------------------------------------
  1277. Total 40.141ns (19.479ns logic, 20.662ns route)
  1278. (48.5% logic, 51.5% route)
  1279.  
  1280. =========================================================================
  1281. Timing constraint: Default OFFSET IN BEFORE for Clock 'divisor<0>'
  1282. Total number of paths / destination ports: 5334 / 99
  1283. -------------------------------------------------------------------------
  1284. Offset: 8.727ns (Levels of Logic = 11)
  1285. Source: divisor<6> (PAD)
  1286. Destination: init_reg.quo_reg_3 (LATCH)
  1287. Destination Clock: divisor<0> falling
  1288.  
  1289. Data Path: divisor<6> to init_reg.quo_reg_3
  1290. Gate Net
  1291. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1292. ---------------------------------------- ------------
  1293. IBUF:I->O 55 0.818 0.708 divisor_6_IBUF (divisor_6_IBUF)
  1294. LUT2:I0->O 18 0.094 1.066 init_reg_quo_reg_mux0031<17>1141 (N922)
  1295. LUT6:I1->O 1 0.094 0.000 init_reg_quo_reg_mux0031<3>1012 (init_reg_quo_reg_mux0031<3>1012)
  1296. MUXF7:I0->O 1 0.251 0.480 init_reg_quo_reg_mux0031<3>101_f7 (init_reg_quo_reg_mux0031<3>101)
  1297. LUT6:I5->O 1 0.094 0.710 init_reg_quo_reg_mux0031<3>168_SW0 (N2046)
  1298. LUT6:I3->O 1 0.094 0.789 init_reg_quo_reg_mux0031<3>168 (init_reg_quo_reg_mux0031<3>168)
  1299. LUT5:I1->O 1 0.094 0.576 init_reg_quo_reg_mux0031<3>224_SW0 (N2048)
  1300. LUT6:I4->O 1 0.094 0.710 init_reg_quo_reg_mux0031<3>224 (init_reg_quo_reg_mux0031<3>224)
  1301. LUT6:I3->O 1 0.094 0.789 init_reg_quo_reg_mux0031<3>283_SW0 (N2002)
  1302. LUT6:I2->O 3 0.094 0.984 init_reg_quo_reg_mux0031<3>283 (init_reg_quo_reg_mux0031<3>283)
  1303. LUT5:I0->O 1 0.094 0.000 init_reg_quo_reg_mux0031<3>293 (init_reg_quo_reg_mux0031<3>)
  1304. LDCP:D -0.071 init_reg.quo_reg_3
  1305. ----------------------------------------
  1306. Total 8.727ns (1.915ns logic, 6.812ns route)
  1307. (21.9% logic, 78.1% route)
  1308.  
  1309. =========================================================================
  1310. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  1311. Total number of paths / destination ports: 64 / 64
  1312. -------------------------------------------------------------------------
  1313. Offset: 3.259ns (Levels of Logic = 1)
  1314. Source: quo_31 (FF)
  1315. Destination: quo<31> (PAD)
  1316. Source Clock: mclk1 rising
  1317.  
  1318. Data Path: quo_31 to quo<31>
  1319. Gate Net
  1320. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1321. ---------------------------------------- ------------
  1322. FD:C->Q 1 0.471 0.336 quo_31 (quo_31)
  1323. OBUF:I->O 2.452 quo_31_OBUF (quo<31>)
  1324. ----------------------------------------
  1325. Total 3.259ns (2.923ns logic, 0.336ns route)
  1326. (89.7% logic, 10.3% route)
  1327.  
  1328. =========================================================================
  1329.  
  1330.  
  1331. Total REAL time to Xst completion: 11666.00 secs
  1332. Total CPU time to Xst completion: 11661.74 secs
  1333.  
  1334. -->
  1335.  
  1336.  
  1337. Total memory usage is 685000 kilobytes
  1338.  
  1339. Number of errors : 0 ( 0 filtered)
  1340. Number of warnings : 109 ( 0 filtered)
  1341. Number of infos : 4 ( 0 filtered)
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