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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- entity control is
- Port (
- Opcode : in std_logic_vector(10 downto 0);
- Reg2Loc : out STD_LOGIC; -- Register 2 Location, Rm (20-16) or Rt/Rd (4-0) field?
- Uncondbranch : out STD_LOGIC; -- PC relative addressing or PC increment by 4?
- CBZ : out STD_LOGIC; -- PC relative addressing or PC increment by 4?
- CBNZ : out STD_LOGIC; -- PC relative addressing or PC increment by 4?
- BR : out std_logic; -- Set PC to value in ALU output
- MemRead : out STD_LOGIC; -- Allows memory to output data at address
- MemWrite : out STD_LOGIC; -- Loads data into memory
- ALUControl : out std_logic_vector(3 downto 0); -- 4 bit output to ALU to determine operation
- ALUSrc : out STD_LOGIC; -- ALU 2nd Operand from register or immediate field?
- MemToReg : out STD_LOGIC; -- Determines if data written to register is from ALU or Memory
- RegWrite : out STD_LOGIC -- Loads data into register
- );
- end control;
- architecture Behavioral of control is
- constant ADD_R : std_logic_vector(10 downto 0) := "10001011000"; -- 11 bits
- constant SUB_R : std_logic_vector(10 downto 0) := "11001011000"; -- 11 bits
- constant LSL_R : std_logic_vector(10 downto 0) := "11010011011"; -- 11 bits
- constant LSR_R : std_logic_vector(10 downto 0) := "11010011010"; -- 11 bits
- constant AND_R : std_logic_vector(10 downto 0) := "10001010000"; -- 11 bits
- constant OR_R : std_logic_vector(10 downto 0) := "10101010000"; -- 11 bits
- constant LDUR_D : std_logic_vector(10 downto 0) := "11111000010"; -- 11 bits
- constant STUR_D : std_logic_vector(10 downto 0) := "11111000000"; -- 11 bits
- constant BR_R : std_logic_vector(10 downto 0) := "11010110000"; -- 11 bits
- constant ADDI_I : std_logic_vector(9 downto 0) := "1001000100"; -- (10 downto 1) bits
- constant SUBI_I : std_logic_vector(9 downto 0) := "1101000100"; -- (10 downto 1) bits
- constant MOVZ_IM : std_logic_vector(8 downto 0) := "110100101"; -- (10 downto 2) bits
- constant CBNZ_CB : std_logic_vector(7 downto 0) := "10110101"; -- (10 downto 3) bits
- constant CBZ_CB : std_logic_vector(7 downto 0) := "10110100"; -- (10 downto 3) bits
- constant B_B : std_logic_vector(5 downto 0) := "000101"; -- (10 downto 5) bits
- begin
- -- Reg2Loc
- Reg2Loc <= '1' when Opcode(10 downto 3) = CBNZ_CB or -- CB format
- Opcode(10 downto 3) = CBZ_CB or
- Opcode(10 downto 2) = MOVZ_IM -- IM format
- else '0';
- -- Uncondbranch
- Uncondbranch <= '1' when Opcode(10 downto 5) = B_B
- else '0';
- -- CBZ
- CBZ <= '1' when Opcode(10 downto 3) = CBZ_CB
- else '0';
- -- CBNZ
- CBNZ <= '1' when Opcode(10 downto 3) = CBNZ_CB
- else '0';
- -- BR
- BR <= '1' when Opcode = BR_R
- else '0';
- -- MemRead
- MemRead <= '1' when Opcode = LDUR_D
- else '0';
- -- MemWrite
- MemWrite <= '1' when Opcode = STUR_D
- else '0';
- -- ALUControl
- ALUControl <= "0000" when Opcode = AND_R else -- AND
- "0001" when Opcode = OR_R else -- OR
- "0010" when Opcode = ADD_R or -- add
- Opcode = LDUR_D or
- Opcode = STUR_D or
- Opcode = BR_R or
- Opcode(10 downto 1) = ADDI_I else
- "0110" when Opcode = SUB_R or -- subtract
- Opcode(10 downto 1) = SUBI_I else
- "1000" when Opcode(10 downto 2) = MOVZ_IM or -- Pass Register 1 (set Z flag)
- Opcode(10 downto 3) = CBNZ_CB or
- Opcode(10 downto 3) = CBZ_CB else
- "1101" when Opcode = LSL_R else -- Shift Left Logical
- "1111" when Opcode = LSR_R -- Shift Right Logical
- else "0010"; -- add
- -- ALUSrc
- ALUSrc <= '1' when Opcode = LSL_R or
- Opcode = LSR_R or
- Opcode = LDUR_D or
- Opcode = STUR_D or
- Opcode(10 downto 1) = ADDI_I or
- Opcode(10 downto 1) = SUBI_I or
- Opcode(10 downto 2) = MOVZ_IM
- else '0';
- -- MemToReg
- MemToReg <= '1' when (Opcode = LDUR_D)
- else '0';
- -- RegWrite
- RegWrite <= '1' when Opcode = ADD_R or
- Opcode = SUB_R or
- Opcode = LSL_R or
- Opcode = LSR_R or
- Opcode = LDUR_D or
- Opcode(10 downto 1) = ADDI_I or
- Opcode(10 downto 1) = SUBI_I or
- Opcode(10 downto 2) = MOVZ_IM or
- Opcode = AND_R or
- Opcode = OR_R
- else '0';
- end Behavioral;
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