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Mikestriken

Control

Apr 7th, 2023 (edited)
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VHDL 5.21 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity control is
  5.     Port (
  6.         Opcode : in std_logic_vector(10 downto 0);
  7.        
  8.         Reg2Loc : out STD_LOGIC; -- Register 2 Location, Rm (20-16) or Rt/Rd (4-0) field?
  9.         Uncondbranch : out STD_LOGIC; -- PC relative addressing or PC increment by 4?
  10.         CBZ : out STD_LOGIC; -- PC relative addressing or PC increment by 4?
  11.         CBNZ : out STD_LOGIC; -- PC relative addressing or PC increment by 4?
  12.         BR : out std_logic; -- Set PC to value in ALU output
  13.         MemRead : out STD_LOGIC; -- Allows memory to output data at address
  14.         MemWrite : out STD_LOGIC; -- Loads data into memory
  15.         ALUControl : out std_logic_vector(3 downto 0); -- 4 bit output to ALU to determine operation
  16.         ALUSrc : out STD_LOGIC; -- ALU 2nd Operand from register or immediate field?
  17.         MemToReg : out STD_LOGIC; -- Determines if data written to register is from ALU or Memory
  18.         RegWrite : out STD_LOGIC -- Loads data into register
  19.     );
  20. end control;
  21.  
  22. architecture Behavioral of control is
  23.     constant ADD_R : std_logic_vector(10 downto 0) := "10001011000"; -- 11 bits
  24.     constant SUB_R : std_logic_vector(10 downto 0) := "11001011000"; -- 11 bits
  25.     constant LSL_R : std_logic_vector(10 downto 0) := "11010011011"; -- 11 bits
  26.     constant LSR_R : std_logic_vector(10 downto 0) := "11010011010"; -- 11 bits
  27.     constant AND_R : std_logic_vector(10 downto 0) := "10001010000"; -- 11 bits
  28.     constant OR_R  : std_logic_vector(10 downto 0) := "10101010000"; -- 11 bits
  29.     constant LDUR_D : std_logic_vector(10 downto 0) := "11111000010"; -- 11 bits
  30.     constant STUR_D : std_logic_vector(10 downto 0) := "11111000000"; -- 11 bits
  31.     constant BR_R  : std_logic_vector(10 downto 0) := "11010110000"; -- 11 bits
  32.     constant ADDI_I : std_logic_vector(9 downto 0) := "1001000100"; -- (10 downto 1) bits
  33.     constant SUBI_I : std_logic_vector(9 downto 0) := "1101000100"; -- (10 downto 1) bits
  34.     constant MOVZ_IM : std_logic_vector(8 downto 0) := "110100101"; -- (10 downto 2) bits
  35.     constant CBNZ_CB : std_logic_vector(7 downto 0) := "10110101"; -- (10 downto 3) bits
  36.     constant CBZ_CB : std_logic_vector(7 downto 0) := "10110100"; -- (10 downto 3) bits
  37.     constant B_B   : std_logic_vector(5 downto 0) := "000101"; -- (10 downto 5) bits
  38. begin
  39.     -- Reg2Loc
  40.     Reg2Loc <= '1' when Opcode(10 downto 3) = CBNZ_CB or -- CB format
  41.                         Opcode(10 downto 3) = CBZ_CB or
  42.                        
  43.                         Opcode(10 downto 2) = MOVZ_IM  -- IM format
  44.                    else '0';
  45.    
  46.     -- Uncondbranch
  47.     Uncondbranch <= '1' when Opcode(10 downto 5) = B_B
  48.                         else '0';
  49.    
  50.     -- CBZ
  51.     CBZ <= '1' when Opcode(10 downto 3) = CBZ_CB
  52.                else '0';
  53.    
  54.     -- CBNZ
  55.     CBNZ <= '1' when Opcode(10 downto 3) = CBNZ_CB
  56.                 else '0';
  57.    
  58.     -- BR
  59.     BR <= '1' when Opcode = BR_R
  60.               else '0';
  61.    
  62.     -- MemRead
  63.     MemRead <= '1' when Opcode = LDUR_D
  64.                    else '0';
  65.  
  66.     -- MemWrite
  67.     MemWrite <= '1' when Opcode = STUR_D
  68.                    else '0';
  69.    
  70.     -- ALUControl
  71.    ALUControl <= "0000" when Opcode = AND_R else -- AND
  72.    
  73.                  "0001" when Opcode = OR_R else -- OR
  74.                  
  75.                  "0010" when Opcode = ADD_R or  -- add
  76.                              Opcode = LDUR_D or
  77.                              Opcode = STUR_D or
  78.                              Opcode = BR_R or
  79.                              Opcode(10 downto 1) = ADDI_I else
  80.                              
  81.                  "0110" when Opcode = SUB_R or  -- subtract
  82.                              Opcode(10 downto 1) = SUBI_I else
  83.                              
  84.                  "1000" when Opcode(10 downto 2) = MOVZ_IM or -- Pass  Register 1 (set Z flag)
  85.                              Opcode(10 downto 3) = CBNZ_CB or
  86.                              Opcode(10 downto 3) = CBZ_CB else
  87.                  
  88.                  "1101" when Opcode = LSL_R else -- Shift Left Logical
  89.                  
  90.                  "1111" when Opcode = LSR_R -- Shift Right Logical
  91.                  
  92.                  else "0010"; -- add
  93.  
  94.    
  95.     -- ALUSrc
  96.     ALUSrc <= '1' when Opcode = LSL_R or
  97.                        Opcode = LSR_R or
  98.                        Opcode = LDUR_D or
  99.                        Opcode = STUR_D or
  100.                        Opcode(10 downto 1) = ADDI_I or
  101.                        Opcode(10 downto 1) = SUBI_I or
  102.                        Opcode(10 downto 2) = MOVZ_IM
  103.                   else '0';
  104.    
  105.     -- MemToReg
  106.     MemToReg <= '1' when (Opcode = LDUR_D)
  107.                     else '0';
  108.    
  109.     -- RegWrite
  110.     RegWrite <= '1' when Opcode = ADD_R or
  111.                          Opcode = SUB_R or
  112.                          Opcode = LSL_R or
  113.                          Opcode = LSR_R or
  114.                          Opcode = LDUR_D or
  115.                          Opcode(10 downto 1) = ADDI_I or
  116.                          Opcode(10 downto 1) = SUBI_I or
  117.                          Opcode(10 downto 2) = MOVZ_IM or
  118.                          Opcode = AND_R or
  119.                          Opcode = OR_R
  120.                     else '0';
  121.    
  122. end Behavioral;
Tags: control
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