library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4 is
    Port ( wej : in  STD_LOGIC_VECTOR(1 downto 0);
           wyj : out  STD_LOGIC_VECTOR(3 downto 0);
           cyfra_1 : in  STD_LOGIC_VECTOR(3 downto 0);
           cyfra_2 : in  STD_LOGIC_VECTOR(3 downto 0);
           cyfra_3 : in  STD_LOGIC_VECTOR(3 downto 0);
           cyfra_4 : in  STD_LOGIC_VECTOR(3 downto 0));
end mux4;

architecture Behavioral of mux4 is

begin
with wej select
wyj <= cyfra_1 when "00",
         cyfra_2 when "01",
         cyfra_3 when "10",
         cyfra_4 when others;



end Behavioral;