CWNoMT.asm

; Patch the Japanese ROM using asar 1.37
; Most of the code was written by SethBling
; Save states by IsoFrieze

lorom

Display0 = $F0
Display1 = $F1
Display2 = $F2
Display3 = $F3
Display4 = $F4
Display5 = $F5

DrawTextMode = $F6
TimerHigh = $F7
TimerLow = $F8
PrevScreen = $F9
TongueCompletionPos = $FB
WasJumping = $FD
ItemSwapPos = $FF

MarioXLow = $D1
MarioXHigh = $D2
MarioYLow = $D3
SpriteX = $E4
MarioFacing = $76
RidingYoshi = $187A
SpriteStatusTable = $14C8

StatusBarTiles = $0EF9

Controller1Byte1 = $4218
Controller1Byte2 = $4219
Controller2Byte1 = $421A
Controller2Byte2 = $421B

; BRK Vector
org $00FFE6
DW BRKVector

ORG $00FF93
BRKVector:
    BRA BRKVector

; Status bar hook
org $008F8A
JSL Start

org $00FFD8
    db $08 ; SRAM Size?

org $00A206
    db $00

org $00D078
    NOP
    NOP
    NOP

org $00C512
    LDA $17
    AND #$30
    BEQ $0D
    BRA $15

;org $01C6B2 ; Chargin Chuck Item Swap Hijack
;   dw $C6B4

org $00FF30
StatusBar:
            JSL MoreWork

            LDA DrawTextMode
            BEQ DrawStatusBar
            RTL

DrawStatusBar:
            LDX #$22
            LDY #$33
StatusBarLoop:
            LDA MemWatch-2,x
            STA $00
            LDA MemWatch-1,x
            STA $01
            LDA [$00]
            AND #$0F
            STA StatusBarTiles-1,y
            LDA [$00]
            LSR A
            LSR A
            LSR A
            LSR A
            STA StatusBarTiles-2,y
            LDA #$FC
            STA StatusBarTiles-3,y
            DEX
            DEX
            DEY
            DEY
            DEY
            BNE StatusBarLoop

SpitPos:
            ; Clear the spit pos display
            LDA #$FC
            STA StatusBarTiles+$33
            STA StatusBarTiles+$34
            STA StatusBarTiles+$35
            STA StatusBarTiles+$36

            ; Prepare the loop to find Yoshi
            LDY #$0A
            LDX RidingYoshi
            BNE SpriteLoop

            RTL

SpriteLoop:
            DEY
            BPL +
            RTL
+
            ; Check if Yoshi has shell in mouth
            LDA SpriteStatusTable,Y
            CMP #$07
            BNE SpriteLoop

            ; Get Position and calculate spit pos
            LDA MarioXLow
            LDX MarioFacing
            CLC
            ADC.L FacingOffset,X

            ; Display spit pos
            PHA
            AND #$0F
            STA StatusBarTiles+$35
            PLA
            LSR A
            LSR A
            LSR A
            LSR A
            STA StatusBarTiles+$34

            RTL

FacingOffset:
            DB  $EE, $12

MemWatch:
            DW SpriteX+0
            DW SpriteX+1
            DW SpriteX+2
            DW SpriteX+3
            DW SpriteX+4
            DW SpriteX+5
            DW Display0
            DW Display1
            DW Display2
            DW $182A
            DW $1829
            DW $0300
            DW $02F4
            DW Controller1Byte1
            DW Controller1Byte2
            DW Controller2Byte1
            DW Controller2Byte2
            DW $00A7 ; Sprite #9 sprite number

org $01AB72 ; Shell Kick Hijack
    JSR TestForBlockDupe

org $01F347 ; Yoshi Tongue Completion Hijack
    JSR YoshiTongueCompletion

org $01FFD0
YoshiTongueCompletion:
    STZ $151C,x
    LDY.b MarioXLow
    STY.b TongueCompletionPos

    RTS

org $01FFDB
TestForBlockDupe:
    JSL TestForBlockDupeFull
    RTS

org $0FF000
TestForBlockDupeFull:
    LDA MarioXHigh
    CMP #$03
    BNE .Wrong
    LDA MarioXLow
    CMP #$6F
    BMI .Wrong
    CMP #$73
    BPL .Wrong
    LDA MarioYLow
    CMP #$4B
    BMI .Wrong
    CMP #$55
    BPL .Wrong
    LDA $7B ; Mario x-velocity
    BNE .NonzeroVelocity

    ; Play "Correct" Sound
    LDA #$29
    STA $1DFC
    BRA .Return

.NonzeroVelocity:
    LDA #$2A
    STA $1DFC
    BRA .Return

.Wrong:
    LDA #$03
    STA $1DF9

.Return:
    RTL

MoreWork:
    JSR CheckFCJump
    RTL

CheckFCJump:
    LDA WasJumping
    CMP $72
    BMI Jumped
    LDA $72
    STA WasJumping
    RTS

Jumped:
    LDA $72
    STA WasJumping

    LDA $95
    CMP #$01
    BNE NotJumpPos
    LDA $96
    CMP #$30
    BNE NotJumpPos
    LDA $94

    CMP #$5C
    BMI NotJumpPos
    CMP #$64
    BPL NotJumpPos


    ; Play "Correct" Sound
    LDA #$29
    STA $1DFC

NotJumpPos:
    RTS

org $06C970
Start:
JSL StatusBar


Code:
        LDA $0DA2 ; byetudlr
        AND #%00100000 ;Select
        BEQ .done

        LDA $0DA4 ; axlr----
        AND #%00010000 ; R
        BEQ .test_load

        JSL activate_save_state
        BRA .done

    .test_load:
        LDA $0DA4 ; axlr----
        AND #%00100000 ;L
        BEQ .done
        JSL activate_load_state

    .done:
        RTL

    activate_save_state:
        LDA #$0E ; swim sound
        STA $1DF9 ; apu i/o
        LDA #$80
        STA $2100 ; force blank
        STZ $4200 ; nmi disable

        JSL go_poverty_save_state

        LDA #$00
        STA $7F9D8B

        BRA .done
    .done:

        LDA #$81
        STA $4200 ; nmi enable
        LDA #$0F
        STA $2100 ; exit force blank
    .cancel:
        RTL

go_poverty_save_state:
        PHP
        REP #$10

        ; save wram $0000-$1FFF to wram $7F9C7B-$7FBC7A
        LDX #$1FFF
    .loop_mirror:
        LDA $7E0000,X
        STA $7F9C7B,X
        DEX
        BPL .loop_mirror

        ; save wram $C680-$C6DF to $707DA0-$707DFF
        LDX #$005F
    .loop_boss:
        LDA $7EC680,X
        STA $707DA0,X
        DEX
        BPL .loop_boss

        ; save wram $7F9A7B-$7F9C7A to $707BA0-$707D9F
        LDX #$01FF
    .loop_wiggler:
        LDA $7F9A7B,X
        STA $707BA0,X
        DEX
        BPL .loop_wiggler

        ; save wram $C800-$FFFF to $700BA0-$70439F
        LDX #$37FF
    .loop_tilemap_low:
        LDA $7EC800,X
        STA $700BA0,X
        DEX
        BPL .loop_tilemap_low

        ; save wram $7FC800-$7FFFFF to $7043A0-$704ADF
        ; since only bit 0 is used for this data, crunch it into a 1:8 ratio
        ; unrolled inner loop is used for the speed increase
        PHB
        LDA #$70
        PHA
        PLB

        LDX #$37F8
        LDY #$06FF
    .loop_tilemap_high:
        LDA $7FC800,X
        STA $00
        LDA $7FC801,X
        STA $01
        LDA $7FC802,X
        STA $02
        LDA $7FC803,X
        STA $03
        LDA $7FC804,X
        STA $04
        LDA $7FC805,X
        STA $05
        LDA $7FC806,X
        STA $06
        LDA $7FC807,X
        STA $07
        LDA #$00
        LSR $00
        ROL A
        LSR $01
        ROL A
        LSR $02
        ROL A
        LSR $03
        ROL A
        LSR $04
        ROL A
        LSR $05
        ROL A
        LSR $06
        ROL A
        LSR $07
        ROL A
        STA $43A0,Y ; $7043A0,Y
        DEX #8
        DEY
        BPL .loop_tilemap_high

        ; do these separately because they actually use the upper 7 bits
        LDX #$001F
    .loop_mode7_bridge_a:
        LDA $7FC8B0,X
        STA $704AA0,X
        DEX
        BPL .loop_mode7_bridge_a

        LDX #$001F
    .loop_mode7_bridge_b:
        LDA $7FCA60,X
        STA $704AC0,X
        DEX
        BPL .loop_mode7_bridge_b

        PLB

        ; save cgram w$00-w$FF to $707E00-$707FFF
        LDA #$00
        STA $2121 ; cgram address
        LDX #$7E00
        STX $4302 ; dma0 destination address
        LDA #$70
        STA $4304 ; dma0 destination bank
        LDX #$0200
        STX $4305 ; dma0 length
        LDA #$80 ; 1-byte
        STA $4300 ; dma0 parameters
        LDA #$3B ; $213B cgram data read
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; save vram w$0000-w$03FF to wram $7FBC7B-$7FC47A
        LDA #$80
        STA $2115 ; vram increment
        LDX #$0000
        STX $2116 ; vram address
        LDX $2139 ; vram data read (dummy read)
        LDX #$BC7B
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$0800
        STX $4305 ; dma0 length
        LDA #$81 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$39 ; $2139 vram data read
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; save vram w$0400-w$06BF to wram $7EC100-$7EC67F
        LDA #$80
        STA $2115 ; vram increment
        LDX #$0400
        STX $2116 ; vram address
        LDX $2139 ; vram data read (dummy read)
        LDX #$C100
        STX $4302 ; dma0 destination address
        LDA #$7E
        STA $4304 ; dma0 destination bank
        LDX #$0580
        STX $4305 ; dma0 length
        LDA #$81 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$39 ; $2139 vram data read
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; save vram w$06C0-w$07FF to wram $7FC47B-$7EC6FA
        LDA #$80
        STA $2115 ; vram increment
        LDX #$06C0
        STX $2116 ; vram address
        LDX $2139 ; vram data read (dummy read)
        LDX #$C47B
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$0280
        STX $4305 ; dma0 length
        LDA #$81 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$39 ; $2139 vram data read
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; save vram w$0800-w$0FFF to wram $7F877B-$7F977A
        LDA #$80
        STA $2115 ; vram increment
        LDX #$0800
        STX $2116 ; vram address
        LDX $2139 ; vram data read (dummy read)
        LDX #$877B
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$1000
        STX $4305 ; dma0 length
        LDA #$81 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$39 ; $2139 vram data read
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; save vram w$1000-w$3FFF to wram $7F0000-$7F5FFF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$1000
        STX $2116 ; vram address
        LDX $2139 ; vram data read (dummy read)
        LDX #$0000
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$6000
        STX $4305 ; dma0 length
        LDA #$81 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$39 ; $2139 vram data read
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; save vram w$5000-w$5FFF to wram $704AE0-$706ADF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$5000
        STX $2116 ; vram address
        LDX $2139 ; vram data read (dummy read)
        LDX #$4AE0
        STX $4302 ; dma0 destination address
        LDA #$70
        STA $4304 ; dma0 destination bank
        LDX #$2000
        STX $4305 ; dma0 length
        LDA #$81 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$39 ; $2139 vram data read
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; save vram w$7000-w$7FFF to wram $7F6000-$7F7FFF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$7000
        STX $2116 ; vram address
        LDX $2139 ; vram data read (dummy read)
        LDX #$6000
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$2000
        STX $4305 ; dma0 length
        LDA #$81 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$39 ; $2139 vram data read
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; save the stack pointer to $7FC7F7 - $7FC7F8
        REP #$30
        TSX
        TXA
        STA $7FC7F7

        ; save the currently used music to $7FC7F9
        SEP #$20
        LDA $2142
        STA $7FC7F9

    .done:
        PLP
        RTL


    activate_load_state:
        LDA #$80
        STA $2100 ; force blank
        STZ $4200 ; nmi disable
        JSL go_poverty_load_state

        BRA .done

    .done:
    redirect_load_state:
        JSL restore_hardware_regs
        LDA #$81
        STA $4200 ; nmi enable

        LDA #$01
        INC A
        ASL #3
        TAX
    .loop:
        DEX
        BEQ .done_waiting
        WAI ; wait for NMI
        STZ $2100
        WAI ; wait for IRQ
        STZ $2100
        BRA .loop

    .done_waiting:
    cancel:
        RTL

go_poverty_load_state:
        PHP

    .increment_load_count
        REP #$20
        LDA $7F9D8B
        INC A
        STA $7F9D8B
        SEP #$20

    .letsgo:

        REP #$10

        ; load wram $7F9C7B-$7FBC7A to wram $0000-$1FFF
        LDX #$1FFF
    .loop_mirror:
        LDA $7F9C7B,X
        STA $7E0000,X
        DEX
        BPL .loop_mirror

        ; load $707DA0-$707DFF to wram $C680-$C6DF
        LDX #$005F
    .loop_boss:
        LDA $707DA0,X
        STA $7EC680,X
        DEX
        BPL .loop_boss

        ; load $707BA0-$707D9F to wram $7F9A7B-$7F9C7A
        LDX #$01FF
    .loop_wiggler:
        LDA $707BA0,X
        STA $7F9A7B,X
        DEX
        BPL .loop_wiggler

        ; load $700BA0-$70439F to wram $C800-$FFFF
        LDX #$37FF
    .loop_tilemap_low:
        LDA $700BA0,X
        STA $7EC800,X
        DEX
        BPL .loop_tilemap_low

        ; load $7043A0-$704ABF to wram $7FC800-$7FFFFF
        ; since only bit 0 is used for this data, expand it into a 8:1 ratio
        ; unrolled inner loop is used for the speed increase
        LDX #$0007
    .loop_prepare_scratch:
        STZ $00,X
        DEX
        BPL .loop_prepare_scratch

        PHB
        LDA #$70
        PHA
        PLB

        LDX #$37F8
        LDY #$06FF
    .loop_tilemap_high:
        LDA $43A0,Y ; $7043A0,Y
        LSR $07
        ROR A
        ROL $07
        LSR $06
        ROR A
        ROL $06
        LSR $05
        ROR A
        ROL $05
        LSR $04
        ROR A
        ROL $04
        LSR $03
        ROR A
        ROL $03
        LSR $02
        ROR A
        ROL $02
        LSR $01
        ROR A
        ROL $01
        LSR $00
        ROR A
        ROL $00
        LDA $00
        STA $7FC800,X
        LDA $01
        STA $7FC801,X
        LDA $02
        STA $7FC802,X
        LDA $03
        STA $7FC803,X
        LDA $04
        STA $7FC804,X
        LDA $05
        STA $7FC805,X
        LDA $06
        STA $7FC806,X
        LDA $07
        STA $7FC807,X
        DEX #8
        DEY
        BPL .loop_tilemap_high

        ; do these separately because they actually use the upper 7 bits
        LDX #$001F
    .loop_mode7_bridge_a:
        LDA $704AA0,X
        STA $7FC8B0,X
        DEX
        BPL .loop_mode7_bridge_a

        LDX #$001F
    .loop_mode7_bridge_b:
        LDA $704AC0,X
        STA $7FCA60,X
        DEX
        BPL .loop_mode7_bridge_b

        PLB

        ; load $707E00-$707FFF to cgram w$00-w$FF
        LDA #$00
        STA $2121 ; cgram address
        LDX #$7E00
        STX $4302 ; dma0 destination address
        LDA #$70
        STA $4304 ; dma0 destination bank
        LDX #$0200
        STX $4305 ; dma0 length
        STZ $4300 ; dma0 parameters
        LDA #$22 ; $2122 cgram data write
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; load wram $7FBC7B-$7FC47A to vram w$0000-w$03FF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$0000
        STX $2116 ; vram address
        LDX #$BC7B
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$0800
        STX $4305 ; dma0 length
        LDA #$01 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$18 ; $2118 vram data write
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; load wram $7EC100-$7EC67F to vram w$0400-w$06BF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$0400
        STX $2116 ; vram address
        LDX #$C100
        STX $4302 ; dma0 destination address
        LDA #$7E
        STA $4304 ; dma0 destination bank
        LDX #$0580
        STX $4305 ; dma0 length
        LDA #$01 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$18 ; $2118 vram data write
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; load wram $7FC47B-$7EC6FA to vram w$06C0-w$07FF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$06C0
        STX $2116 ; vram address
        LDX #$C47B
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$0280
        STX $4305 ; dma0 length
        LDA #$01 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$18 ; $2118 vram data write
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; load wram $7F877B-$7F977A to vram w$0800-w$0FFF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$0800
        STX $2116 ; vram address
        LDX #$877B
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$1000
        STX $4305 ; dma0 length
        LDA #$01 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$18 ; $2118 vram data write
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; load wram $7F0000-$7F5FFF to vram w$1000-w$3FFF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$1000
        STX $2116 ; vram address
        LDX #$0000
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$6000
        STX $4305 ; dma0 length
        LDA #$01 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$18 ; $2118 vram data write
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; load wram $704AE0-$706ADF to vram w$5000-w$5FFF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$5000
        STX $2116 ; vram address
        LDX #$4AE0
        STX $4302 ; dma0 destination address
        LDA #$70
        STA $4304 ; dma0 destination bank
        LDX #$2000
        STX $4305 ; dma0 length
        LDA #$01 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$18 ; $2118 vram data write
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; load wram $7F6000-$7F7FFF to vram w$7000-w$7FFF
        LDA #$80
        STA $2115 ; vram increment
        LDX #$7000
        STX $2116 ; vram address
        LDX #$6000
        STX $4302 ; dma0 destination address
        LDA #$7F
        STA $4304 ; dma0 destination bank
        LDX #$2000
        STX $4305 ; dma0 length
        LDA #$01 ; 2-byte, low-high
        STA $4300 ; dma0 parameters
        LDA #$18 ; $2118 vram data write
        STA $4301 ; dma0 source
        LDA #$01 ; channel 0
        STA $420B ; dma enable

        ; load the stack pointer from $7FC7F7 - $7FC7F8
        REP #$30
        LDA $7FC7F7
        TAX
        TXS

        ; load the currently used music from $7FC7F9
        SEP #$20
        LDA $7FC7F9
        CMP $2142
        BEQ .same_music
        STA $2142
    .same_music:
        REP #$20

        ; since we restored the stack, we need to update the return
        ; address of this routine to what we want it to be. otherwise,
        ; it would return to the save state routine.
        LDX #redirect_load_state-1
        TXA
        STA $02,S

    .done:
        PLP
        RTL

    restore_hardware_regs:
        LDA $0DB0 ; mosaic mirror
        ORA #$03
        STA $2106 ; mosaic

        LDA $0D9D ; tm mirror
        STA $212C ; tm
        STA $212E ; tmw
        LDA $0D9E ; ts mirror
        STA $212D ; ts
        STA $212F ; tsw

        LDA #$23 ; sometimes #$59 ($008416)
        STA $2107 ; gb1sc
        LDA #$33
        STA $2108 ; gb2sc
        LDA #$53
        STA $2109 ; gb3sc
        LDA #$00 ; sometimes #$07 ($008416)
        STA $210B ; bg12nba
        LDA #$04
        STA $210C ; bg34nba
        RTL