DMC-aware delay code

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; Delays A:X clocks+overhead
; Time: 256*A+X+33 clocks (including JSR)
; Written by Joel Yliluoma. Clobbers A. Preserves X,Y. Has relocations.
; This part is verified to work correctly.
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:       ; do 256 cycles.        ; 5 cycles done so far. Loop is 2+1+ 2+3+ 1 = 9 bytes.
        sbc #1                  ; 2 cycles - Carry was set from cmp
        pha                     ; 3 cycles
         lda #(256-25-10-2-4)   ; +2
         jsr delay_a_25_clocks
        pla                     ; 4 cycles
delay_256a_x_33_clocks:
        cmp #1                  ; +2; 2 cycles overhead
        Jcs :-                  ; +2; 4 cycles overhead
        ; 0-255 cycles remain, overhead = 4
        txa                     ; +2; 6; +27 = 33
        ; 15 + JSR + RTS overhead for the code below. JSR=6, RTS=6. 15+12=27
        ;          ;    Cycles        Accumulator     Carry flag
        ;          ; 0  1  2  3  4       (hex)        0 1 2 3 4
        sec        ; 0  0  0  0  0   00 01 02 03 04   1 1 1 1 1
:       sbc #5     ; 2  2  2  2  2   FB FC FD FE FF   0 0 0 0 0
        Jcs :-     ; 4  4  4  4  4   FB FC FD FE FF   0 0 0 0 0
        lsr a      ; 6  6  6  6  6   7D 7E 7E 7F 7F   1 0 1 0 1
        Jcc :+     ; 8  8  8  8  8   7D 7E 7E 7F 7F   1 0 1 0 1
:       sbc #$7E   ;10 11 10 11 10   FF FF 00 00 01   0 0 1 1 1
        Jcc :+     ;12 13 12 13 12   FF FF 00 00 01   0 0 1 1 1
        Jeq :+     ;      14 15 14         00 00 01       1 1 1
        Jne :+     ;            16               01           1
:       rts        ;15 16 17 18 19   (thanks to dclxvi for the algorithm)
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; Delays A clocks + overhead
; Preserved: X, Y
; Time: A+25 clocks (including JSR)  (13+6+6)
; This part is verified to work correctly.
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:       sbc #7          ; carry set by CMP
delay_a_25_clocks:
    cmp #7      ;2
    Jcs :-          ;2    do multiples of 7
    ;               ; Cycles          Accumulator            Carry           Zero
    lsr a           ; 0 0 0 0 0 0 0   00 01 02 03 04 05 06   0 0 0 0 0 0 0   ? ? ? ? ? ? ?
    Jcs :+          ; 2 2 2 2 2 2 2   00 00 01 01 02 02 03   0 1 0 1 0 1 0   1 1 0 0 0 0 0
:       Jeq @zero       ; 4 5 4 5 4 5 4   00 00 01 01 02 02 03   0 1 0 1 0 1 0   1 1 0 0 0 0 0
    lsr a           ; : : 6 7 6 7 6   :: :: 01 01 02 02 03   : : 0 1 0 1 0   : : 0 0 0 0 0
    Jeq :+          ; : : 8 9 8 9 8   :: :: 00 00 01 01 01   : : 1 1 0 0 1   : : 1 1 0 0 0
    Jcc :+          ; : : : : A B A   :: :: :: :: 01 01 01   : : : : 0 0 1   : : : : 0 0 0
@zero:  Jne :+          ; 7 8 : : : : C   00 01 :: :: :: :: 01   0 1 : : : : 1   1 1 : : : : 0
:       rts             ; 9 A B C D E F   00 01 00 00 01 01 01   0 1 1 1 0 0 1   1 1 1 1 0 0 0
; ^ (thanks to dclxvi for the algorithm)


; Input: X:A = number of cycles to delay
; Overhead: 80 cycles
; For use in Castlevania II.
PCMawareDelay:
    ; Sound_PCMsampleActive may be:
    ;      #$00 = no PCM sound
    ;      #$5D = something   0E 7F F3 17  WaveLength=71 or 65, Count=$7F, Addr=$FCC0, Len=369 (ends at $FE31)
    ;      #$5E = something   0F 00 F0 0B  WaveLength=53 or 49, Count=$00, Addr=$FC00, Len=177 (ends at $FCB1)
    ;      #$5F = something   0F 00 F9 0A  WaveLength=53 or 49, Count=$00, Addr=$FE40, Len=161 (ends at $FEE1)
    ;
    ;NTSC:
    ; Sample 5D:     Ratio: 71*8/4 = 568/4 = 142 (3-4 cycles stolen from SPRDMA)
    ; Samples 5E,5F: Ratio: 53*8/4 = 424/4 = 106 (3-4 cycles stolen from SPRDMA)
    ;PAL:
    ; Sample 5D:     Ratio: 65*8/4 = 520/4 = 130 (3-4 cycles stolen from SPRDMA)
    ; Samples 5E,5F: Ratio: 49*8/4 = 392/4 =  98 (3-4 cycles stolen from SPRDMA)

    sta delay_ptr+0     ;3
    stx delay_ptr+1     ;3

    .if PAL=0
        LEN_5D    = 142
        LEN_other = 106
    .else
        LEN_5D    = 130
        LEN_other = 98
    .endif
    STEAL=1

@pcm_loop:
    lda $4015       ;4
    and #$10        ;2
    Jeq @no_pcm     ;3 = 15
                ;-1
    lda Sound_PCMsampleActive ;4
    cmp #$5D        ;2
    Jeq @pcm_5D     ;3
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@pcm_other:         ;-1, 22 so far
    ldy #LEN_other      ;2
    Jne @pcm_common     ;3, 27
@pcm_5D:            ; 23 so far
    ldy #LEN_5D     ;2, 25
    nop         ;+2 to balance the cycles
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@pcm_common:            ; 27 so far
    lda delay_ptr+1     ;3
    Jne @pcm_ok_quick   ;3 = 33
                ;-1
    cpy delay_ptr+0     ;3
    Jcs @trailer        ;3 = 38
                ;-1
    Jcc @pcm_ok     ;3 = 40

@pcm_ok_quick:          ; 33 so far
    php
    plp         ;+7
@pcm_ok:            ; 40 so far
    lda delay_ptr+0     ;3
    sty delay_ptr+0     ;3
    sec         ;2
    sbc delay_ptr+0     ;3
    sta delay_ptr+0     ;3
    lda delay_ptr+1     ;3
    sbc #0          ;2
    sta delay_ptr+1     ;3
    tya         ;2
    sbc #(25+63+STEAL)  ;2   ; the "63" from below goes here.
    jsr delay_a_25_clocks   ;0
    jmp @pcm_loop       ;3 = 69, MINUS 6 from beginning = 63 per loop

@no_pcm:                ;15 so far
    php
    plp ;+7
    php
    plp ;+7
    php
    plp ;+7
    nop ;+2   = +23
@trailer:               ;38 so far
    lda delay_ptr+1         ;3
    ldx delay_ptr+0         ;3
    jmp delay_256a_x_33_clocks  ;3
    ; Total overhead: 40+3+3+3 + 33 = 80 cycles.

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