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- ***** Spice Netlist for Cell 'srxtest' *****
- ************** Module srxtest **************
- vdd n0 n1 dc='5' ac='0'
- v0 n1 gnd dc='0' ac='0'
- mpull1 bit read n0 n0 PMOS4 w='2.0u' l='0.4u' m='1'
- mpull2 bitb read n0 n0 PMOS4 w='2.0u' l='0.4u' m='1'
- vread read n1 pulse 0 5v 0ns 200ps 200ps 3ns 6ns
- vdd1 n2 gnd dc='0' ac='0'
- mpulldown1 bit write gnd gnd NMOS4 w='1.5u' l='0.4u' m='1'
- mpulldown2 bitb writeb gnd gnd NMOS4 w='1.5u' l='0.4u' m='1'
- vwrite write gnd pulse 0 5v 0ns 200ps 200ps 3ns 6ns
- vwriteb writeb gnd pulse 0 5v 0ns 200ps 200ps 3ns 6ns
- vsense en gnd pulse 0 5v 0ns 200ps 200ps 3ns 6ns
- vwl wl n1 pulse 0 5v 0ns 200ps 200ps 3ns 6ns
- mpull3 bitb read bit n0 PMOS4 w='2.0u' l='0.4u' m='1'
- c0 n1 bit 1280f
- c1 n1 bitb 1280f
- mbit bit n1 n1 n1 NMOS4 w='0.8u' l='0.4u' m='127'
- mbitb n1 n1 bitb n1 NMOS4 w='0.8u' l='0.4u' m='127'
- mwlgnd n1 wl n1 n1 NMOS4 w='0.8u' l='0.4u' m='256'
- mwlvdd n0 wl n0 n1 NMOS4 w='0.8u' l='0.4u' m='256'
- c2 n1 wl 2560f
- xi0 wl bit bitb n0 n1 6T_1
- xi1 en bit dout bitb gnd n2 senseamp
- ************** Module 6T_1 **************
- .subckt 6T_1 wl bit bitb vdd gnd example_param=1.0
- m0 n0 n1 vdd vdd PMOS4 w='0.6u' l='0.8u' m='1'
- m1 vdd n0 n1 vdd PMOS4 w='0.6u' l='0.8u' m='1'
- m2 gnd n0 n1 gnd NMOS4 w='1.6u' l='0.4u' m='1'
- m3 n0 n1 gnd gnd NMOS4 w='1.6u' l='0.4u' m='1'
- m4 bit wl n1 gnd NMOS4 w='0.8u' l='0.4u' m='1'
- m5 n0 wl bitb gnd NMOS4 w='0.8u' l='0.4u' m='1'
- .ends 6T_1
- ************** Module senseamp **************
- .subckt senseamp en bit dout bitb gnd vdd example_param=1.0
- m0 n1 en gnd gnd NMOS4 w='1.8u' l='0.4u' m='1'
- m1 n1 n0 dout gnd NMOS4 w='1.8u' l='0.4u' m='1'
- m2 n0 dout n1 gnd NMOS4 w='1.8u' l='0.4u' m='1'
- m3 vdd n0 dout vdd PMOS4 w='3.6u' l='0.4u' m='1'
- m4 n0 dout vdd vdd PMOS4 w='3.6u' l='0.4u' m='1'
- m5 bit en dout vdd PMOS4 w='4.8u' l='0.4u' m='1'
- m6 n0 en bitb vdd PMOS4 w='4.8u' l='0,4u' m='1'
- .ends senseamp
- .end
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