Lab08 - Ej01 - Testbench

module testbench();

    reg A, B, Cin;
    wire S, Cout;

    full_adder U1(A, B, Cin, S, Cout);

    initial begin
        $display("Cin A B | S Cout");
        $display("----------------");
        $monitor("  %b %b %b | %b  %b", Cin, A, B, S, Cout);
        Cin = 0; A = 0; B = 0;
        #1
        Cin = 0; A = 0; B = 1;
        #1
        Cin = 0; A = 1; B = 0;
        #1
        Cin = 0; A = 1; B = 1;
        #1
        Cin = 1; A = 0; B = 0;
        #1
        Cin = 1; A = 0; B = 1;
        #1
        Cin = 1; A = 1; B = 0;
        #1
        Cin = 1; A = 1; B = 1;
        #1
        $finish;
    end

endmodule