vga.sv

// File name     : vga.sv
// Description   : vga monitor's generator
// URL           : http://www.pyroelectro.com
// Author        : Chris@PyroElectro.com
// Version       : 1.0
// Last revision : 04.10.2021

// Made by       : Anatoly Sharapov as stepfather
// Aged          : 47
// Email         : a.a.sharapov@gmail.com
// Phone         : +7 903 231-11-26

// Made for      : Anja Solodjanikova as stepdaughter
// Aged          : 6

`include "../Headers/vga.svh"
`include "../Headers/RZ-EazyFPGA_A2.2.svh"

module vga (

    input logic clk50MHz,   // Input clock
    input logic resetn,     // Global reset - active negative

    // VGA Signals/Pins (Outputs)

    output logic hsync,
    output logic vsync,

    output logic red,
    output logic green,
    output logic blue,

    output logic `LEDS_UNPACKED_ARRAY_PINS_RNG led

);

    logic `LEDS_PACKED_ARRAY_CNT_RNG led_cnt;
    always_ff @(posedge clk25_175MHz)
        led_cnt <= !resetn ? '0 : led_cnt + 1'b1;

    assign led = led_cnt[`LEDS_PACKED_ARRAY_CNT_WDT-1:
                           `LEDS_PACKED_ARRAY_CNT_WDT-`LEDS_UNPACKED_ARRAY_PINS_WDT];

    logic clk25_175MHz;

    vga_pll vga_pll_inst (

        .inclk0 ( clk50MHz      ),    // 50 MHz
        .c0     ( clk25_175MHz  )     // 25,175 MHz

    );

    // Video Enables
    logic video_en,
          horizontal_en,
          vertical_en;

    // Color Signals
    logic red_signal,
          green_signal,
          blue_signal;

    // Sync Signals
    logic hsync_signal,
          vsync_signal;

    //Sync Counters
    logic `CNT_RNG h_cnt,
                   v_cnt;

    assign video_en = horizontal_en & vertical_en;

    always_ff @(posedge clk25_175MHz) begin

        // -----------------  Horizontal Sync ---------------

        // Horizontal Counter
        h_cnt <= !resetn || h_cnt == `WHOLE_LINE_PXLS - 1 ? '0 : h_cnt + 1'b1;

        // Generate Horizontal Data
        // Rows Of Red
        if (v_cnt >= 0 && v_cnt < `FIRST_HORIZ_BORDER_PXLS) begin
            red_signal   <= 1'b1;
            green_signal <= 1'b0;
            blue_signal  <= 1'b0;
        end;

        // Rows Of Green
        if (v_cnt >= `FIRST_HORIZ_BORDER_PXLS && v_cnt < `SECOND_HORIZ_BORDER_PXLS) begin
            red_signal   <= 1'b0;
            green_signal <= 1'b1;
            blue_signal  <= 1'b0;
        end;

        // Rows Of Blue
        if (v_cnt >= `SECOND_HORIZ_BORDER_PXLS && v_cnt <= `VISIBLE_FRAME_PXLS) begin
            red_signal   <= 1'b0;
            green_signal <= 1'b0;
            blue_signal  <= 1'b1;
        end;

        // Generate Horizontal Sync
        hsync_signal <= h_cnt >= `HORIZ_SYNC_PRE_PXLS && h_cnt <= `HORIZ_SYNC_POST_PXLS;

        // -----------------  Vertical Sync ---------------

        // Reset Vertical Counter

        v_cnt <= !resetn ||
                 v_cnt > `VERT_FRAME_PXLS - 2 &&
                 h_cnt > `WHOLE_LINE_PXLS - 2 ? '0 :
                 h_cnt == `WHOLE_LINE_PXLS ?
                 v_cnt + 1'b1 :
                 v_cnt;

        // Generate Vertical Sync
        vsync_signal <= v_cnt > `VERT_SYNC_PRE_PXLS && v_cnt < `VERT_SYNC_POST_PXLS;

        // Generate Horizontal Enable
        horizontal_en <= h_cnt < `VISIBLE_LINE_PXLS;

        // Generate Vertical Enable
        vertical_en <= v_cnt < `VISIBLE_FRAME_PXLS;

        // Assign Physical Signals To VGA
        red   <= red_signal   & video_en;
        green <= green_signal & video_en;
        blue  <= blue_signal  & video_en;

    end // always_ff @(posedge clk25_175MHz) begin

    `ifdef VGA640X480

        assign hsync = ~hsync_signal;
        assign vsync = ~vsync_signal;

    `elsif VGA1280X1024

        assign hsync = hsync_signal;
        assign vsync = vsync_signal;

    `else // defaulf - for test purposes

        assign hsync = 1'b1;
        assign vsync = 1'b0;

    `endif

endmodule : vga