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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- --(a) izgradnja dekodera 1/2
- -- warning: this file will not be saved if:
- -- * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
- -- * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
- ENTITY dekoder12 IS port (
- e, a: in std_logic;
- y0, y1 : out std_logic );
- END dekoder12;
- ARCHITECTURE arch OF dekoder12 IS
- BEGIN
- y0 <= e and not a after 10 ns;
- y1 <= e and a after 10 ns;
- END arch;
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