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Doda94

dekoder12

Dec 4th, 2023
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VHDL 0.58 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. --(a) izgradnja dekodera 1/2
  4. -- warning: this file will not be saved if:
  5. --     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
  6. --     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
  7. ENTITY dekoder12 IS port (
  8.     e, a: in std_logic;
  9.     y0, y1 : out std_logic );
  10. END dekoder12;
  11.        
  12. ARCHITECTURE arch OF dekoder12 IS
  13.    
  14. BEGIN
  15.     y0 <= e and not a after 10 ns;
  16.     y1 <= e and a after 10 ns;
  17. END arch;
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