module Layer #(parameter num_inps=2)(out, inps, ws, clk, rst);
    output reg out;
    input real inps[num_inps];
    input logic clk, rst;
    input real ws[num_inps];
    real temp[num_inps];
    int j;
    genvar i;
    generate
        for(i=0; i<num_inps; i++) begin
            assign temp[i] = inps[i] * ws[i];
        end
    endgenerate
    always @( posedge clk, posedge rst) begin : res
        $display("inps: ", inps[0], " ", inps[1]);
        $display("ws: ", ws[0], " ", ws[1]);
        $display("temp: ", temp[0], " ", temp[1]);
        if (rst==1) begin
            $display("oopsie did a rest :(");
            out <= 0;
        end
        else begin
            out = 0;
            begin
                for(j=0; j<num_inps; j++) begin
                    out <= out + temp[j];
                    $display(temp[j]);
                end
            end
        end
    end
endmodule