//code

module dlatch(
    input logic d,
    input logic en,
    input logic rst,
    output logic q
    );


    always@(en or rst or d)
    if(rst)
    q<=0;
    else
    if(en)
    q<=d;
endmodule


//testbench

module dlatch_tb();
logic d, en, rst;
logic q;

dlatch uut(d, en , rst, q);
initial begin
rst = 1; en =0; d =0;
#10
rst = 0; en = 0; d=1;
#10
rst=0; en = 1; d=1;
#10
$finish;
end
endmodule