ARM_Meminterface_almostdone

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--	Schnittstelle zur Anbindung des RAM an die Busse des HWPR-Prozessors
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--	Datum:		??.??.2013
--	Version:	?.?
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.ArmConfiguration.all;
use work.ArmTypes.all;

entity ArmMemInterface is
	generic(
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--	Beide Generics sind fuer das HWPR nicht relevant und koennen von
--	Ihnen ignoriert werden.
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		SELECT_LINES				: natural range 0 to 2 := 1;
		EXTERNAL_ADDRESS_DECODING_INSTRUCTION : boolean := false);
	port (  RAM_CLK	:  in  std_logic;
		--	Instruction-Interface
       		IDE		:  in std_logic;
			IA		:  in std_logic_vector(31 downto 2);
			ID		: out std_logic_vector(31 downto 0);
			IABORT	: out std_logic;
		--	Data-Interface
			DDE		:  in std_logic;
			DnRW	:  in std_logic;
			DMAS	:  in std_logic_vector(1 downto 0);
			DA 		:  in std_logic_vector(31 downto 0);
			DDIN	:  in std_logic_vector(31 downto 0);
			DDOUT	: out std_logic_vector(31 downto 0);
			DABORT	: out std_logic);
end entity ArmMemInterface;

architecture behave of ArmMemInterface is

type ram_type is array(4095 downto 0) of std_logic_vector(31 downto 0);
shared variable RAM : ram_type;
signal WEB : std_logic_vector(3 downto 0);
signal abort : std_logic := ('0') ;

begin

    WEB <=  "0011" when (DMAS = "01" and DA(1 downto 0) = "00") else
            "1100" when (DMAS = "01" and DA(1 downto 0) = "11") else
            "0001" when (DMAS = "00" and DA(1 downto 0) = "00") else
            "0010" when (DMAS = "00" and DA(1 downto 0) = "01") else
            "0100" when (DMAS = "00" and DA(1 downto 0) = "10") else
            "1000" when (DMAS = "00" and DA(1 downto 0) = "11") else
            "1111" when (DMAS = "10" and DA(1 downto 0) = "00");

    ram_inst : entity work.ArmRAMB_4kx32(behavioral)
    port map(
        RAM_CLK => RAM_CLK,
        ENA => IDE,
        ADDRA => IA(13 downto 2),
        WEB => WEB,
        DOA => ID,
        DIB => DDIN,
        ENB => DDE,
        ADDRB => DA(13 downto 2)
    );

     instruction_bus : process(IDE, IA)
     begin
        if ( IDE = '1' ) then
            if( IA >= INST_LOW_ADDR and IA <= INST_HIGH_ADDR) then
                IABORT <= '0';
                ID <= RAM(to_integer(unsigned(IA)));
            else
                IABORT <= '1';
                ID <= (others => 'Z');
            end if;
        else
            ID <= (others => 'Z');
            IABORT <= 'Z';
        end if;
     end process;

    daten_bus : process(DDE, DA, DnRW, DMAS)
    begin
    if((DDE = '1') and (DnRW = '0')) then
        DDOUT <= RAM(to_integer(unsigned(DA(31 downto 2))));
    else
        DDOUT <= (others => 'Z');
    end if;
    if((DDE = '1') and (DnRW = '1')) then
        if (DMAS = "11") then
            abort <= '1';
        end if;
    end if;
    if((DDE = '1') and (DnRW = '1')) then
        if (DMAS = "11") then
            abort <= '1';
        elsif(DMAS = "01") then
            if(DA(1 downto 0) = "00" or DA(1 downto 0) = "10") then
                abort <= '0';
            else
                abort <= '1';
            end if;
        elsif(DMAS = "10") then
            if(DA(1 downto 0) = "00") then
                abort <= '0';
            else
                abort <= '1';
            end if;
        end if;
        if(abort = '0') then
            RAM(to_integer(unsigned(DA))) := DDIN;
        end if;
    end if;
    DABORT <= abort;
    end process;
end architecture behave;