Lab08 - Ej04 - ALU & Testbench

module alu (input [3:0] A, B, input [2:0] F, output [3:0] Y);

    reg [3:0] rY;

    always @ (A or B or F) begin
        case (F)
            3'b000: rY = A & B;
            3'b001: rY = A | B;
            3'b010: rY = A + B;
            3'b100: rY = A & ~B;
            3'b101: rY = A | ~B;
            3'b110: rY = A - B;
            3'b111: begin
                if (A >= B)
                    rY = 4'b0000;
                else
                    rY = 4'b0001;
            end
            default: rY = 4'b0000;
        endcase
    end

    assign Y = rY;

endmodule

module testbench();

    reg [3:0] A, B;
    reg [2:0] F;

    wire [3:0] Y;

    alu U1(A, B, F, Y);

    initial begin
        $display("F\tA\tB\tY");
        $monitor("%b\t%b\t%b\t%b", F, A, B, Y);
        F = 3'b000; A = 4'b0110; B = 4'b0010;
        #1
        F = 3'b001; A = 4'b1100; B = 4'b0001;
        #1
        F = 3'b010; A = 4'b0111; B = 4'b0001;
        #1
        F = 3'b011; A = 4'b1010; B = 4'b0101;
        #1
        F = 3'b100; A = 4'b0101; B = 4'b1010;
        #1
        F = 3'b101; A = 4'b1100; B = 4'b0011;
        #1
        F = 3'b110; A = 4'b0111; B = 4'b0001;
        #1
        F = 3'b111; A = 4'b0011; B = 4'b0001;
        #1
        A = 4'b0010; B = 4'b1000;
    end
endmodule