XOR

library IEEE;
use IEEE.std_logic_1164.all;

entity xor_vhdl is

    port(A1 : in std_logic;
         A2 : in std_logic;
         X1 : out std_logic);

end xor_vhdl;

architecture logic of xor_vhdl is

 begin

     X1 <= A1 xor A2;

end logic;