module main_tb();
real out;
real inps[2], ws[2];
logic clk, rst;
Layer l1(out, inps, ws, clk, rst);
initial begin
    $dumpfile("target/ow.vcd");
    $dumpvars(0, main_tb);
    inps[0] = 1.0;
    inps[1] = 2.0;
    ws[0] = 5.0;
    ws[1] = 3.0;
    rst = 0;
    clk = 0;
    #10
    clk = 1;
    #10
    clk = 0;
    $display(out);
    #10
    $finish;
end
endmodule