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- -- design.vhd
- library IEEE;
- use IEEE.std_logic_1164.all;
- entity jk_flipflop_async is
- port(J, K : in std_logic;
- Q, Qn : out std_logic);
- end entity jk_flipflop_async;
- architecture jk_flipflop_async_arch of jk_flipflop_async is
- begin
- process(J, K)
- begin
- if(J = '0' and K = '0') then
- Q <= Q;
- Qn <= Qn;
- elsif(J = '0' and K = '1') then
- Q <= '0';
- Qn <= '1';
- elsif(J = '1' and K = '0') then
- Q <= '1';
- Qn <= '0';
- elsif(J = '1' and K = '1') then
- Q <= Qn;
- Qn <= Q;
- else
- Q <= 'Z';
- Qn <= 'Z';
- end if;
- end process;
- end architecture jk_flipflop_async_arch;
- -- testbench.vhd
- library IEEE;
- use IEEE.std_logic_1164.all;
- entity jk_flipflop_async_tb is
- end entity jk_flipflop_async_tb;
- architecture jk_flipflop_async_tb_arch of jk_flipflop_async_tb is
- signal J, K, Q, Qn : std_logic;
- begin
- DUT1 : entity work.jk_flipflop_async(jk_flipflop_async_arch)
- port map(J, K, Q, Qn);
- STIMULUS : process
- begin
- J <= '0'; K <= '0'; wait for 10ns;
- J <= '1'; K <= '0'; wait for 10ns;
- J <= '0'; K <= '1'; wait for 10ns;
- J <= '1'; K <= '1'; wait for 10ns;
- J <= 'X'; K <= 'X'; wait for 10ns;
- end process STIMULUS;
- end architecture jk_flipflop_async_tb_arch;
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