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JK FLIP-FLOP ASYNC

Apr 30th, 2023
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VHDL 1.37 KB | Source Code | 0 0
  1. -- design.vhd
  2.  
  3. library IEEE;
  4. use IEEE.std_logic_1164.all;
  5.  
  6. entity jk_flipflop_async is
  7.     port(J, K : in std_logic;
  8.          Q, Qn : out std_logic);
  9. end entity jk_flipflop_async;
  10.  
  11. architecture jk_flipflop_async_arch of jk_flipflop_async is
  12. begin
  13.     process(J, K)
  14.     begin
  15.         if(J = '0' and K = '0') then
  16.             Q <= Q;
  17.             Qn <= Qn;
  18.         elsif(J = '0' and K = '1') then
  19.             Q <= '0';
  20.             Qn <= '1';
  21.         elsif(J = '1' and K = '0') then
  22.             Q <= '1';
  23.             Qn <= '0';
  24.         elsif(J = '1' and K = '1') then
  25.             Q <= Qn;
  26.             Qn <= Q;
  27.         else
  28.             Q <= 'Z';
  29.             Qn <= 'Z';
  30.         end if;
  31.     end process;
  32. end architecture jk_flipflop_async_arch;
  33.  
  34. -- testbench.vhd
  35.  
  36. library IEEE;
  37. use IEEE.std_logic_1164.all;
  38.  
  39. entity jk_flipflop_async_tb is
  40. end entity jk_flipflop_async_tb;
  41.  
  42. architecture jk_flipflop_async_tb_arch of jk_flipflop_async_tb is
  43.     signal J, K, Q, Qn : std_logic;
  44. begin
  45.     DUT1 : entity work.jk_flipflop_async(jk_flipflop_async_arch)
  46.            port map(J, K, Q, Qn);
  47.     STIMULUS : process
  48.     begin
  49.         J <= '0'; K <= '0'; wait for 10ns;
  50.         J <= '1'; K <= '0'; wait for 10ns;
  51.         J <= '0'; K <= '1'; wait for 10ns;
  52.         J <= '1'; K <= '1'; wait for 10ns;
  53.         J <= 'X'; K <= 'X'; wait for 10ns;
  54.     end process STIMULUS;
  55. end architecture jk_flipflop_async_tb_arch;
Tags: VHDL
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