Program_Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity program_counter is
    port (
        clk     : in  std_logic;
        rst     : in  std_logic; -- reset
        pc_in   : in  std_logic_vector(63 downto 0);
        pc_out  : out std_logic_vector(63 downto 0)
    );
end entity program_counter;

architecture behavioral of program_counter is
    signal pc_reg : std_logic_vector(63 downto 0);
begin
    -- Clock logic
    process (clk)
    begin
        if rst = '1' then
            pc_reg <= (others => '0');
        elsif rising_edge(clk) then
            pc_reg <= pc_in;
        end if;
    end process;

    -- Signal Assignment
    pc_out <= pc_reg;
end architecture behavioral;