Funkcija

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY funkcija IS port(
    a: in std_logic;
    b: in std_logic;
    c: in std_logic;
    d: in std_logic;
    f: out std_logic);
END funkcija;

ARCHITECTURE arch OF funkcija IS
    signal tmp1 : std_logic;
    signal tmp2 : std_logic_vector(0 to 3);
    signal tmp3 : std_logic_vector(0 to 15);
BEGIN
    tmp1 <= '1';
    tmp2 <= a & b & c & d;
    c1: entity work.dek416e port map (tmp1, tmp2, tmp3);
    f <= tmp3(0) or tmp3(2) or tmp3(3) or tmp3(5) or tmp3(6) or tmp3(7) or tmp3(9) or tmp3(10) or tmp3(11) or tmp3(12);

END arch;