Lab08 - Ej02

`include "full_adder.v"

module rca (input [3:0] A, B, input Cin, output [3:0] S, output Cout);

    wire FA1_to_FA2, FA2_to_FA3, FA3_to_FA4;

    full_adder U1(A[0], B[0], Cin, S[0], FA1_to_FA2);
    full_adder U2(.A(A[1]), .B(B[1]), .Cin(FA1_to_FA2), .S(S[1]), .Cout(FA2_to_FA3)); // Otra forma de hacer las interconexiones
    full_adder U3(.S(S[2]), .Cout(FA3_to_FA4), .Cin(FA2_to_FA3), .B(B[2]), .A(A[2]));
    full_adder U4(A[3], B[3], FA3_to_FA4, S[3], Cout);


endmodule

module testbench();

    reg [3:0] A, B;
    reg Cin;
    wire [3:0] S;
    wire Cout;

    rca U1(A, B, Cin, S, Cout);

    initial begin
        $display("Cin\tA\tB    |\tS\tCout");
        $display("------------------------------------");
        $monitor("%b\t%b\t%b |\t%b\t%b", Cin, A, B, S, Cout);
        A = 0; B = 0; Cin = 0;
        #1
        A = 1; B = 1; Cin = 0;
        #1
        Cin = 1; A = 1; B = 1;
        #1
        Cin = 0; A = 15; B = 1;
        #1
        Cin = 0; A = 15; B = 2;
        #1
        Cin = 1; A = 15; B = 1;
        #1
        Cin = 1; A = 4; B = 4;
        #1
        Cin = 0; A = 1; B = 15;
        #1
        Cin = 1; A = 1; B = 15;
        #1
        Cin = 1; A = 5; B = 7;
    end

endmodule