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  1. #include "am5729-beagleboneai.dts"
  2.  
  3. &{/chosen} {
  4.     base_dtb = "bbai-custom.dts";   // <-- name of this file goes here
  5. };
  6.  
  7. #define P9_11A  ( 0x3400 + 4 * 203 )
  8. #define P9_11B  ( 0x3400 + 4 * 136 )
  9. #define P9_13A  ( 0x3400 + 4 * 204 )
  10.  
  11. &dra7_pmx_core {
  12.     uart5_pins: uart5 {
  13.         pinctrl-single,pins = <
  14.             DRA7XX_CORE_IOPAD( P9_13A, PIN_OUTPUT       | MUX_MODE4  ) // txd
  15.             DRA7XX_CORE_IOPAD( P9_11A, PIN_INPUT_PULLUP | MUX_MODE4  ) // rxd
  16.             DRA7XX_CORE_IOPAD( P9_11B, PIN_OUTPUT       | MUX_MODE15 ) // (shared pin)
  17.         >;
  18.     };
  19. };
  20.  
  21.  
  22. // ttyS4
  23. &uart5 {
  24.     status = "okay";
  25.     pinctrl-names = "default";
  26.     pinctrl-0 = <&uart5_pins>;
  27. };
  28.  
  29. // Here's the obnoxious part: since u-boot doesn't have sane pin defaults yet, all pins not  
  30. // explicitly setup above should be overridden here.  This will eventually no longer be needed.  
  31. &cape_pins_default {
  32.     pinctrl-single,pins = <
  33.     //  DRA7XX_CORE_IOPAD( 0x372C, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // P9.11a (no gpio)  
  34.     //  DRA7XX_CORE_IOPAD( 0x3620, PIN_INPUT          | MUX_MODE14 )  // P9.11b
  35.         DRA7XX_CORE_IOPAD( 0x36AC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.12 
  36.     //  DRA7XX_CORE_IOPAD( 0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // P9.13a (no gpio)  
  37.         DRA7XX_CORE_IOPAD( 0x35AC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.14 
  38.         DRA7XX_CORE_IOPAD( 0x3514, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.15 
  39.         DRA7XX_CORE_IOPAD( 0x35B0, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.16 
  40.         DRA7XX_CORE_IOPAD( 0x37CC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.17a
  41.         DRA7XX_CORE_IOPAD( 0x36B8, PIN_INPUT          | MUX_MODE14 )  // P9.17b
  42.         DRA7XX_CORE_IOPAD( 0x37C8, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.18a
  43.         DRA7XX_CORE_IOPAD( 0x36B4, PIN_INPUT          | MUX_MODE14 )  // P9.18b
  44.         DRA7XX_CORE_IOPAD( 0x3440, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P9.19a
  45.         DRA7XX_CORE_IOPAD( 0x357C, PIN_INPUT          | MUX_MODE14 )  // P9.19b
  46.         DRA7XX_CORE_IOPAD( 0x3444, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P9.20a
  47.         DRA7XX_CORE_IOPAD( 0x3578, PIN_INPUT          | MUX_MODE14 )  // P9.20b
  48.         DRA7XX_CORE_IOPAD( 0x34F0, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.21a
  49.         DRA7XX_CORE_IOPAD( 0x37C4, PIN_INPUT          | MUX_MODE14 )  // P9.21b
  50.         DRA7XX_CORE_IOPAD( 0x369C, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.22a
  51.         DRA7XX_CORE_IOPAD( 0x37C0, PIN_INPUT          | MUX_MODE14 )  // P9.22b
  52.         DRA7XX_CORE_IOPAD( 0x37B4, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P9.23 
  53.         DRA7XX_CORE_IOPAD( 0x368C, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P9.24  can rx
  54.         DRA7XX_CORE_IOPAD( 0x3694, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.25 
  55.         DRA7XX_CORE_IOPAD( 0x3688, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P9.26a can tx
  56.         DRA7XX_CORE_IOPAD( 0x3544, PIN_INPUT          | MUX_MODE14 )  // P9.26b (unused shared pin)
  57.         DRA7XX_CORE_IOPAD( 0x35A0, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.27a
  58.         DRA7XX_CORE_IOPAD( 0x36B0, PIN_INPUT          | MUX_MODE14 )  // P9.27b
  59.         DRA7XX_CORE_IOPAD( 0x36E0, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.28 
  60.         DRA7XX_CORE_IOPAD( 0x36D8, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.29a
  61.         DRA7XX_CORE_IOPAD( 0x36A8, PIN_INPUT          | MUX_MODE14 )  // P9.29b
  62.         DRA7XX_CORE_IOPAD( 0x36DC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.30 
  63.         DRA7XX_CORE_IOPAD( 0x36D4, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.31a
  64.         DRA7XX_CORE_IOPAD( 0x36A4, PIN_INPUT          | MUX_MODE14 )  // P9.31b
  65.         DRA7XX_CORE_IOPAD( 0x36A0, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.41a
  66.         DRA7XX_CORE_IOPAD( 0x3580, PIN_INPUT          | MUX_MODE14 )  // P9.41b
  67.         DRA7XX_CORE_IOPAD( 0x36E4, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P9.42a
  68.         DRA7XX_CORE_IOPAD( 0x359C, PIN_INPUT          | MUX_MODE14 )  // P9.42b
  69.         DRA7XX_CORE_IOPAD( 0x379C, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.3  
  70.         DRA7XX_CORE_IOPAD( 0x37A0, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.4  
  71.         DRA7XX_CORE_IOPAD( 0x378C, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.5  
  72.         DRA7XX_CORE_IOPAD( 0x3790, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.6  
  73.         DRA7XX_CORE_IOPAD( 0x36EC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.7  
  74.         DRA7XX_CORE_IOPAD( 0x36F0, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.8  
  75.         DRA7XX_CORE_IOPAD( 0x3698, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.9  
  76.         DRA7XX_CORE_IOPAD( 0x36E8, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.10 
  77.         DRA7XX_CORE_IOPAD( 0x3510, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.11 
  78.         DRA7XX_CORE_IOPAD( 0x350C, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.12 
  79.         DRA7XX_CORE_IOPAD( 0x3590, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.13 
  80.         DRA7XX_CORE_IOPAD( 0x3598, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.14 
  81.         DRA7XX_CORE_IOPAD( 0x3570, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.15a
  82.         DRA7XX_CORE_IOPAD( 0x35B4, PIN_INPUT          | MUX_MODE14 )  // P8.15b
  83.         DRA7XX_CORE_IOPAD( 0x35BC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.16 
  84.         DRA7XX_CORE_IOPAD( 0x3624, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.17 
  85.         DRA7XX_CORE_IOPAD( 0x3588, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.18 
  86.         DRA7XX_CORE_IOPAD( 0x358C, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.19 
  87.         DRA7XX_CORE_IOPAD( 0x3780, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.20 
  88.         DRA7XX_CORE_IOPAD( 0x377C, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.21 
  89.         DRA7XX_CORE_IOPAD( 0x3798, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.22 
  90.         DRA7XX_CORE_IOPAD( 0x3794, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.23 
  91.         DRA7XX_CORE_IOPAD( 0x3788, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.24 
  92.         DRA7XX_CORE_IOPAD( 0x3784, PIN_INPUT_PULLUP   | MUX_MODE14 )  // P8.25 
  93.         DRA7XX_CORE_IOPAD( 0x35B8, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.26 
  94.         DRA7XX_CORE_IOPAD( 0x35D8, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.27a
  95.         DRA7XX_CORE_IOPAD( 0x3628, PIN_INPUT          | MUX_MODE14 )  // P8.27b
  96.         DRA7XX_CORE_IOPAD( 0x35C8, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.28a
  97.         DRA7XX_CORE_IOPAD( 0x362C, PIN_INPUT          | MUX_MODE14 )  // P8.28b
  98.         DRA7XX_CORE_IOPAD( 0x35D4, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.29a
  99.         DRA7XX_CORE_IOPAD( 0x3630, PIN_INPUT          | MUX_MODE14 )  // P8.29b
  100.         DRA7XX_CORE_IOPAD( 0x35CC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.30a
  101.         DRA7XX_CORE_IOPAD( 0x3634, PIN_INPUT          | MUX_MODE14 )  // P8.30b
  102.         DRA7XX_CORE_IOPAD( 0x3614, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.31a
  103.         DRA7XX_CORE_IOPAD( 0x373C, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // P8.31b (no gpio)  
  104.         DRA7XX_CORE_IOPAD( 0x3618, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.32a
  105.         DRA7XX_CORE_IOPAD( 0x3740, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // P8.32b (no gpio)  
  106.         DRA7XX_CORE_IOPAD( 0x3610, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.33a
  107.         DRA7XX_CORE_IOPAD( 0x34E8, PIN_INPUT          | MUX_MODE14 )  // P8.33b
  108.         DRA7XX_CORE_IOPAD( 0x3608, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.34a
  109.         DRA7XX_CORE_IOPAD( 0x3564, PIN_INPUT          | MUX_MODE14 )  // P8.34b
  110.         DRA7XX_CORE_IOPAD( 0x360C, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.35a
  111.         DRA7XX_CORE_IOPAD( 0x34E4, PIN_INPUT          | MUX_MODE14 )  // P8.35b
  112.         DRA7XX_CORE_IOPAD( 0x3604, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.36a
  113.         DRA7XX_CORE_IOPAD( 0x3568, PIN_INPUT          | MUX_MODE14 )  // P8.36b
  114.         DRA7XX_CORE_IOPAD( 0x35FC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.37a
  115.         DRA7XX_CORE_IOPAD( 0x3738, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // P8.37b (no gpio)  
  116.         DRA7XX_CORE_IOPAD( 0x3600, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.38a
  117.         DRA7XX_CORE_IOPAD( 0x3734, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // P8.38b (no gpio)  
  118.         DRA7XX_CORE_IOPAD( 0x35F4, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.39 
  119.         DRA7XX_CORE_IOPAD( 0x35F8, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.40 
  120.         DRA7XX_CORE_IOPAD( 0x35EC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.41 
  121.         DRA7XX_CORE_IOPAD( 0x35F0, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.42 
  122.         DRA7XX_CORE_IOPAD( 0x35E4, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.43 
  123.         DRA7XX_CORE_IOPAD( 0x35E8, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.44 
  124.         DRA7XX_CORE_IOPAD( 0x35DC, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.45a
  125.         DRA7XX_CORE_IOPAD( 0x361C, PIN_INPUT          | MUX_MODE14 )  // P8.45b
  126.         DRA7XX_CORE_IOPAD( 0x35E0, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P8.46a
  127.         DRA7XX_CORE_IOPAD( 0x3638, PIN_INPUT          | MUX_MODE14 )  // P8.46b
  128.     >;
  129. };
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