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vedic_div32.syr.cd9c4efd19a8ea7a3c44c65ad62d7f605819830e

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May 11th, 2015
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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 0.00 secs
  8. Total CPU time to Xst completion: 0.07 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 0.00 secs
  15. Total CPU time to Xst completion: 0.07 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-1-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : YES
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Off
  74. Reduce Control Sets : Off
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 1
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" in Library work.
  115. Architecture rtl of Entity vedic_div32 is up to date.
  116.  
  117. =========================================================================
  118. * Design Hierarchy Analysis *
  119. =========================================================================
  120. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  121.  
  122.  
  123. =========================================================================
  124. * HDL Analysis *
  125. =========================================================================
  126. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  127. WARNING:Xst:2096 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 81: Use of null array slice on signal <d_init_re_reg> is not supported.
  128. INFO:Xst:2679 - Register <d_init_quo_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  129. INFO:Xst:2679 - Register <init_reg.re_reg<35>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  130. INFO:Xst:2679 - Register <init_reg.re_reg<34>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  131. INFO:Xst:2679 - Register <init_reg.re_reg<33>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  132. INFO:Xst:2679 - Register <init_reg.re_reg<32>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  133. INFO:Xst:2679 - Register <init_reg.re_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  134. INFO:Xst:2679 - Register <init_reg.re_reg<0>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  135. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  136.  
  137.  
  138. =========================================================================
  139. * HDL Synthesis *
  140. =========================================================================
  141.  
  142. Performing bidirectional port resolution...
  143.  
  144. Synthesizing Unit <vedic_div32>.
  145. Related source file is "/home/calros/enshu3-vedicdivider/vedic_div32.vhd".
  146. WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
  147. WARNING:Xst:646 - Signal <d_state> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  148. WARNING:Xst:646 - Signal <d_re> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  149. WARNING:Xst:1780 - Signal <d_init_re_reg<31>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  150. WARNING:Xst:646 - Signal <d_init_re_reg<30:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  151. WARNING:Xst:646 - Signal <d_init_quo_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  152. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  153. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  154. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  155. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  156. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  157. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  158. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  159. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  160. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  161. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  162. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  163. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  164. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  165. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  166. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  167. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  168. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  169. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  170. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  171. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  172. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  173. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  174. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  175. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  176. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  177. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  178. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  179. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  180. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  181. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  182. Found finite state machine <FSM_0> for signal <state>.
  183. -----------------------------------------------------------------------
  184. | States | 4 |
  185. | Transitions | 9 |
  186. | Inputs | 3 |
  187. | Outputs | 4 |
  188. | Clock | mclk1 (rising_edge) |
  189. | Reset | state$and0000 (positive) |
  190. | Reset type | synchronous |
  191. | Reset State | fin_state |
  192. | Power Up State | init_state |
  193. | Encoding | automatic |
  194. | Implementation | LUT |
  195. -----------------------------------------------------------------------
  196. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  197. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  198. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  199. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  200. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  201. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  202. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  203. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  204. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  205. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  206. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  207. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  208. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  209. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  210. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  211. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  212. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  213. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  214. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  215. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  216. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  217. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  218. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  219. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  220. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  221. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  222. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  223. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  224. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  225. WARNING:Xst:737 - Found 5-bit latch for signal <shift_val>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  226. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  227. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  228. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  229. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  230. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  231. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  232. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  233. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  234. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  235. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  236. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  237. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  238. WARNING:Xst:737 - Found 31-bit latch for signal <b_n>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  239. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  240. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  241. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  242. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  243. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  244. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  245. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  246. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  247. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  248. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  249. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  250. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  251. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  252. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_31>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  253. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  254. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  255. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  256. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  257. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  258. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  259. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  260. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 120: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  261. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  262. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  263. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  264. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  265. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  266. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  267. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  268. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  269. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 119: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  270. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  271. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  272. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  273. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 202: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  274. Found 34x4-bit multiplier for signal <$mult0000> created at line 202.
  275. Found 34x5-bit multiplier for signal <$mult0001> created at line 202.
  276. Found 34x5-bit multiplier for signal <$mult0002> created at line 202.
  277. Found 34x5-bit multiplier for signal <$mult0003> created at line 202.
  278. Found 5-bit register for signal <i>.
  279. Found 5-bit subtractor for signal <i$addsub0000> created at line 150.
  280. Found 32-bit register for signal <i_quo>.
  281. Found 32-bit register for signal <i_re>.
  282. Found 32-bit register for signal <k_reg.quo>.
  283. Found 36-bit register for signal <k_reg.re_reg>.
  284. Found 1-bit register for signal <k_reg.re_sign>.
  285. Found 32-bit register for signal <main_reg.quo>.
  286. Found 32-bit addsub for signal <main_reg.quo$mux0000>.
  287. Found 32-bit register for signal <main_reg.quo_reg>.
  288. Found 32-bit adder for signal <main_reg.quo_reg$addsub0000> created at line 133.
  289. Found 1-bit register for signal <main_reg.quo_sign>.
  290. Found 36-bit register for signal <main_reg.re_reg>.
  291. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 136.
  292. Found 36-bit adder for signal <main_reg.re_reg$share0000>.
  293. Found 1-bit register for signal <main_reg.re_sign>.
  294. Found 32-bit addsub for signal <quo$share0000>.
  295. Found 33-bit subtractor for signal <quo_reg_sub$sub0000> created at line 121.
  296. Found 33x32-bit multiplier for signal <quo_tmp$mult0001> created at line 119.
  297. Found 32-bit comparator greatequal for signal <re$cmp_ge0000> created at line 202.
  298. Found 32-bit comparator greatequal for signal <re$cmp_ge0001> created at line 202.
  299. Found 32-bit comparator greatequal for signal <re$cmp_ge0002> created at line 202.
  300. Found 32-bit comparator greatequal for signal <re$cmp_ge0003> created at line 202.
  301. Found 32-bit comparator greatequal for signal <re$cmp_ge0004> created at line 202.
  302. Found 32-bit comparator greatequal for signal <re$cmp_ge0005> created at line 202.
  303. Found 32-bit comparator greatequal for signal <re$cmp_ge0006> created at line 202.
  304. Found 32-bit comparator greatequal for signal <re$cmp_ge0007> created at line 202.
  305. Found 32-bit comparator greatequal for signal <re$cmp_ge0008> created at line 202.
  306. Found 32-bit comparator greatequal for signal <re$cmp_ge0009> created at line 202.
  307. Found 32-bit comparator greatequal for signal <re$cmp_ge0010> created at line 202.
  308. Found 32-bit comparator greatequal for signal <re$cmp_ge0011> created at line 202.
  309. Found 32-bit comparator greatequal for signal <re$cmp_ge0012> created at line 202.
  310. Found 32-bit comparator greatequal for signal <re$cmp_ge0013> created at line 202.
  311. Found 32-bit comparator greatequal for signal <re$cmp_ge0014> created at line 202.
  312. Found 32-bit comparator greatequal for signal <re$cmp_ge0015> created at line 202.
  313. Found 33x4-bit multiplier for signal <re$mult0004> created at line 202.
  314. Found 33x4-bit multiplier for signal <re$mult0005> created at line 202.
  315. Found 33x4-bit multiplier for signal <re$mult0006> created at line 202.
  316. Found 33x3-bit multiplier for signal <re$mult0007> created at line 202.
  317. Found 33x3-bit multiplier for signal <re$mult0008> created at line 202.
  318. Found 33x4-bit multiplier for signal <re$mult0009> created at line 202.
  319. Found 33x4-bit multiplier for signal <re$mult0010> created at line 202.
  320. Found 33x4-bit multiplier for signal <re$mult0011> created at line 202.
  321. Found 32-bit addsub for signal <re$share0000>.
  322. Found 32-bit adder for signal <re$sub0000> created at line 202.
  323. Found 32-bit adder for signal <re$sub0001> created at line 202.
  324. Found 32-bit adder for signal <re$sub0002> created at line 202.
  325. Found 32-bit adder for signal <re$sub0003> created at line 202.
  326. Found 32-bit adder for signal <re$sub0004> created at line 202.
  327. Found 32-bit adder for signal <re$sub0005> created at line 202.
  328. Found 32-bit adder for signal <re$sub0006> created at line 202.
  329. Found 37-bit subtractor for signal <re_reg_sub$sub0000> created at line 122.
  330. Found 33x32-bit multiplier for signal <re_tmp$mult0001> created at line 120.
  331. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 120.
  332. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 120.
  333. Found 32-bit register for signal <tmp_quo_reg>.
  334. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_0$mux0000> created at line 107.
  335. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_1$mux0000> created at line 107.
  336. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_2$mux0000> created at line 107.
  337. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_3$mux0000> created at line 107.
  338. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_4$mux0000> created at line 107.
  339. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_5$mux0000> created at line 107.
  340. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_6$mux0000> created at line 107.
  341. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_7$mux0000> created at line 107.
  342. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_8$mux0000> created at line 107.
  343. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_shifted_0$mux0000> created at line 109.
  344. Found 36-bit adder for signal <v_re$addsub0000> created at line 191.
  345. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 195.
  346. Found 1-bit 32-to-1 multiplexer for signal <v_reg.quo_reg_30$mux0000> created at line 117.
  347. Summary:
  348. inferred 1 Finite State Machine(s).
  349. inferred 272 D-type flip-flop(s).
  350. inferred 16 Adder/Subtractor(s).
  351. inferred 14 Multiplier(s).
  352. inferred 16 Comparator(s).
  353. inferred 42 Multiplexer(s).
  354. inferred 1 Combinational logic shifter(s).
  355. Unit <vedic_div32> synthesized.
  356.  
  357. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
  358.  
  359. =========================================================================
  360. HDL Synthesis Report
  361.  
  362. Macro Statistics
  363. # Multipliers : 14
  364. 33x3-bit multiplier : 2
  365. 33x32-bit multiplier : 2
  366. 33x4-bit multiplier : 6
  367. 34x4-bit multiplier : 1
  368. 34x5-bit multiplier : 3
  369. # Adders/Subtractors : 16
  370. 32-bit adder : 8
  371. 32-bit addsub : 3
  372. 33-bit subtractor : 1
  373. 36-bit adder : 2
  374. 37-bit subtractor : 1
  375. 5-bit subtractor : 1
  376. # Registers : 43
  377. 1-bit register : 35
  378. 32-bit register : 5
  379. 36-bit register : 2
  380. 5-bit register : 1
  381. # Latches : 64
  382. 1-bit latch : 62
  383. 31-bit latch : 1
  384. 5-bit latch : 1
  385. # Comparators : 16
  386. 32-bit comparator greatequal : 16
  387. # Multiplexers : 42
  388. 1-bit 31-to-1 multiplexer : 1
  389. 1-bit 32-to-1 multiplexer : 41
  390. # Logic shifters : 1
  391. 36-bit shifter arithmetic right : 1
  392. # Xors : 1
  393. 1-bit xor2 : 1
  394.  
  395. =========================================================================
  396.  
  397. =========================================================================
  398. * Advanced HDL Synthesis *
  399. =========================================================================
  400.  
  401. Analyzing FSM <FSM_0> for best encoding.
  402. Optimizing FSM <state/FSM> on signal <state[1:4]> with one-hot encoding.
  403. ------------------------
  404. State | Encoding
  405. ------------------------
  406. init_state | 0001
  407. main_state | 0100
  408. wait_state | 1000
  409. fin_state | 0010
  410. ------------------------
  411.  
  412. Synthesizing (advanced) Unit <vedic_div32>.
  413. The following registers are absorbed into accumulator <main_reg.quo>: 1 register on signal <main_reg.quo>.
  414. Unit <vedic_div32> synthesized (advanced).
  415.  
  416. =========================================================================
  417. Advanced HDL Synthesis Report
  418.  
  419. Macro Statistics
  420. # FSMs : 1
  421. # Multipliers : 14
  422. 33x3-bit multiplier : 2
  423. 33x32-bit multiplier : 2
  424. 33x4-bit multiplier : 6
  425. 34x4-bit multiplier : 1
  426. 34x5-bit multiplier : 3
  427. # Adders/Subtractors : 15
  428. 32-bit adder : 8
  429. 32-bit addsub : 2
  430. 33-bit subtractor : 1
  431. 36-bit adder : 2
  432. 37-bit subtractor : 1
  433. 5-bit subtractor : 1
  434. # Accumulators : 1
  435. 32-bit updown loadable accumulator : 1
  436. # Registers : 239
  437. Flip-Flops : 239
  438. # Latches : 64
  439. 1-bit latch : 62
  440. 31-bit latch : 1
  441. 5-bit latch : 1
  442. # Comparators : 16
  443. 32-bit comparator greatequal : 16
  444. # Multiplexers : 42
  445. 1-bit 31-to-1 multiplexer : 1
  446. 1-bit 32-to-1 multiplexer : 41
  447. # Logic shifters : 1
  448. 36-bit shifter arithmetic right : 1
  449. # Xors : 1
  450. 1-bit xor2 : 1
  451.  
  452. =========================================================================
  453.  
  454. =========================================================================
  455. * Low Level Synthesis *
  456. =========================================================================
  457. WARNING:Xst:2677 - Node <Mmult_quo_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  458. WARNING:Xst:2677 - Node <Mmult_re_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  459.  
  460. Optimizing unit <vedic_div32> ...
  461.  
  462. Mapping all equations...
  463. Building and optimizing final netlist ...
  464. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 19.
  465.  
  466. Final Macro Processing ...
  467.  
  468. =========================================================================
  469. Final Register Report
  470.  
  471. Macro Statistics
  472. # Registers : 274
  473. Flip-Flops : 274
  474.  
  475. =========================================================================
  476.  
  477. =========================================================================
  478. * Partition Report *
  479. =========================================================================
  480.  
  481. Partition Implementation Status
  482. -------------------------------
  483.  
  484. No Partitions were found in this design.
  485.  
  486. -------------------------------
  487.  
  488. =========================================================================
  489. * Final Report *
  490. =========================================================================
  491. Final Results
  492. RTL Top Level Output File Name : vedic_div32.ngr
  493. Top Level Output File Name : vedic_div32
  494. Output Format : NGC
  495. Optimization Goal : Speed
  496. Keep Hierarchy : No
  497.  
  498. Design Statistics
  499. # IOs : 130
  500.  
  501. Cell Usage :
  502. # BELS : 6040
  503. # GND : 1
  504. # INV : 249
  505. # LUT1 : 5
  506. # LUT2 : 624
  507. # LUT3 : 320
  508. # LUT4 : 787
  509. # LUT5 : 364
  510. # LUT6 : 1471
  511. # MUXCY : 1153
  512. # MUXF7 : 119
  513. # VCC : 1
  514. # XORCY : 946
  515. # FlipFlops/Latches : 372
  516. # FD : 184
  517. # FDE : 73
  518. # FDR : 2
  519. # FDS : 15
  520. # LDC : 1
  521. # LDCP : 97
  522. # Clock Buffers : 2
  523. # BUFG : 1
  524. # BUFGP : 1
  525. # IO Buffers : 129
  526. # IBUF : 65
  527. # OBUF : 64
  528. # DSPs : 6
  529. # DSP48E : 6
  530. =========================================================================
  531.  
  532. Device utilization summary:
  533. ---------------------------
  534.  
  535. Selected Device : 5vlx50tff1136-1
  536.  
  537.  
  538. Slice Logic Utilization:
  539. Number of Slice Registers: 372 out of 28800 1%
  540. Number of Slice LUTs: 3820 out of 28800 13%
  541. Number used as Logic: 3820 out of 28800 13%
  542.  
  543. Slice Logic Distribution:
  544. Number of LUT Flip Flop pairs used: 3897
  545. Number with an unused Flip Flop: 3525 out of 3897 90%
  546. Number with an unused LUT: 77 out of 3897 1%
  547. Number of fully used LUT-FF pairs: 295 out of 3897 7%
  548. Number of unique control sets: 107
  549.  
  550. IO Utilization:
  551. Number of IOs: 130
  552. Number of bonded IOBs: 130 out of 480 27%
  553.  
  554. Specific Feature Utilization:
  555. Number of BUFG/BUFGCTRLs: 2 out of 32 6%
  556. Number of DSP48Es: 6 out of 48 12%
  557.  
  558. ---------------------------
  559. Partition Resource Summary:
  560. ---------------------------
  561.  
  562. No Partitions were found in this design.
  563.  
  564. ---------------------------
  565.  
  566.  
  567. =========================================================================
  568. TIMING REPORT
  569.  
  570. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  571. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  572. GENERATED AFTER PLACE-and-ROUTE.
  573.  
  574. Clock Information:
  575. ------------------
  576. -----------------------------------+------------------------+-------+
  577. Clock Signal | Clock buffer(FF name) | Load |
  578. -----------------------------------+------------------------+-------+
  579. mclk1 | BUFGP | 274 |
  580. divisor<0> | IBUF+BUFG | 98 |
  581. -----------------------------------+------------------------+-------+
  582.  
  583. Asynchronous Control Signals Information:
  584. ----------------------------------------
  585. --------------------------------------------------------------+--------------------------+-------+
  586. Control Signal | Buffer(FF name) | Load |
  587. --------------------------------------------------------------+--------------------------+-------+
  588. b_n_0__and0000(b_n_0__and00001:O) | NONE(b_n_0) | 1 |
  589. b_n_0__and0001(b_n_0__and00011:O) | NONE(b_n_0) | 1 |
  590. b_n_10__and0000(b_n_10__and00001:O) | NONE(b_n_10) | 1 |
  591. b_n_10__and0001(b_n_10__and00011:O) | NONE(b_n_10) | 1 |
  592. b_n_11__and0000(b_n_11__and00001:O) | NONE(b_n_11) | 1 |
  593. b_n_11__and0001(b_n_11__and00011:O) | NONE(b_n_11) | 1 |
  594. b_n_12__and0000(b_n_12__and00001:O) | NONE(b_n_12) | 1 |
  595. b_n_12__and0001(b_n_12__and00011:O) | NONE(b_n_12) | 1 |
  596. b_n_13__and0000(b_n_13__and00001:O) | NONE(b_n_13) | 1 |
  597. b_n_13__and0001(b_n_13__and00011:O) | NONE(b_n_13) | 1 |
  598. b_n_14__and0000(b_n_14__and00001:O) | NONE(b_n_14) | 1 |
  599. b_n_14__and0001(b_n_14__and00011:O) | NONE(b_n_14) | 1 |
  600. b_n_15__and0000(b_n_15__and00001:O) | NONE(b_n_15) | 1 |
  601. b_n_15__and0001(b_n_15__and00011:O) | NONE(b_n_15) | 1 |
  602. b_n_16__and0000(b_n_16__and00001:O) | NONE(b_n_16) | 1 |
  603. b_n_16__and0001(b_n_16__and00011:O) | NONE(b_n_16) | 1 |
  604. b_n_17__and0000(b_n_17__and00001:O) | NONE(b_n_17) | 1 |
  605. b_n_17__and0001(b_n_17__and00011:O) | NONE(b_n_17) | 1 |
  606. b_n_18__and0000(b_n_18__and00001:O) | NONE(b_n_18) | 1 |
  607. b_n_18__and0001(b_n_18__and00011:O) | NONE(b_n_18) | 1 |
  608. b_n_19__and0000(b_n_19__and00001:O) | NONE(b_n_19) | 1 |
  609. b_n_19__and0001(b_n_19__and00011:O) | NONE(b_n_19) | 1 |
  610. b_n_1__and0000(b_n_1__and00001:O) | NONE(b_n_1) | 1 |
  611. b_n_1__and0001(b_n_1__and00011:O) | NONE(b_n_1) | 1 |
  612. b_n_20__and0000(b_n_20__and00001:O) | NONE(b_n_20) | 1 |
  613. b_n_20__and0001(b_n_20__and00011:O) | NONE(b_n_20) | 1 |
  614. b_n_21__and0000(b_n_21__and00001:O) | NONE(b_n_21) | 1 |
  615. b_n_21__and0001(b_n_21__and00011:O) | NONE(b_n_21) | 1 |
  616. b_n_22__and0000(b_n_22__and00001:O) | NONE(b_n_22) | 1 |
  617. b_n_22__and0001(b_n_22__and00011:O) | NONE(b_n_22) | 1 |
  618. b_n_23__and0000(b_n_23__and00001:O) | NONE(b_n_23) | 1 |
  619. b_n_23__and0001(b_n_23__and00011:O) | NONE(b_n_23) | 1 |
  620. b_n_24__and0000(b_n_24__and00001:O) | NONE(b_n_24) | 1 |
  621. b_n_24__and0001(b_n_24__and00011:O) | NONE(b_n_24) | 1 |
  622. b_n_25__and0000(b_n_25__and00001:O) | NONE(b_n_25) | 1 |
  623. b_n_25__and0001(b_n_25__and00011:O) | NONE(b_n_25) | 1 |
  624. b_n_26__and0000(b_n_26__and00001:O) | NONE(b_n_26) | 1 |
  625. b_n_26__and0001(b_n_26__and00011:O) | NONE(b_n_26) | 1 |
  626. b_n_27__and0000(b_n_27__and00001:O) | NONE(b_n_27) | 1 |
  627. b_n_27__and0001(b_n_27__and00011:O) | NONE(b_n_27) | 1 |
  628. b_n_28__and0000(b_n_28__and00001:O) | NONE(b_n_28) | 1 |
  629. b_n_28__and0001(b_n_28__and00011:O) | NONE(b_n_28) | 1 |
  630. b_n_29__and0000(b_n_29__and00001:O) | NONE(b_n_29) | 1 |
  631. b_n_29__and0001(b_n_29__and00011:O) | NONE(b_n_29) | 1 |
  632. b_n_2__and0000(b_n_2__and00001:O) | NONE(b_n_2) | 1 |
  633. b_n_2__and0001(b_n_2__and00011:O) | NONE(b_n_2) | 1 |
  634. b_n_30__and0000(b_n_30__and00001:O) | NONE(b_n_30) | 1 |
  635. b_n_30__and0001(b_n_30__and00011:O) | NONE(b_n_30) | 1 |
  636. b_n_3__and0000(b_n_3__and00001:O) | NONE(b_n_3) | 1 |
  637. b_n_3__and0001(b_n_3__and00011:O) | NONE(b_n_3) | 1 |
  638. b_n_4__and0000(b_n_4__and00001:O) | NONE(b_n_4) | 1 |
  639. b_n_4__and0001(b_n_4__and00011:O) | NONE(b_n_4) | 1 |
  640. b_n_5__and0000(b_n_5__and00001:O) | NONE(b_n_5) | 1 |
  641. b_n_5__and0001(b_n_5__and00011:O) | NONE(b_n_5) | 1 |
  642. b_n_6__and0000(b_n_6__and00001:O) | NONE(b_n_6) | 1 |
  643. b_n_6__and0001(b_n_6__and00011:O) | NONE(b_n_6) | 1 |
  644. b_n_7__and0000(b_n_7__and00001:O) | NONE(b_n_7) | 1 |
  645. b_n_7__and0001(b_n_7__and00011:O) | NONE(b_n_7) | 1 |
  646. b_n_8__and0000(b_n_8__and00001:O) | NONE(b_n_8) | 1 |
  647. b_n_8__and0001(b_n_8__and00011:O) | NONE(b_n_8) | 1 |
  648. b_n_9__and0000(b_n_9__and00001:O) | NONE(b_n_9) | 1 |
  649. b_n_9__and0001(b_n_9__and00011:O) | NONE(b_n_9) | 1 |
  650. b_n_or0000(b_n_or0000177:O) | NONE(init_reg.quo_reg_31)| 1 |
  651. init_reg.quo_reg_0__and0000(init_reg.quo_reg_0__and00001:O) | NONE(init_reg.quo_reg_0) | 1 |
  652. init_reg.quo_reg_0__and0001(init_reg.quo_reg_0__and00011:O) | NONE(init_reg.quo_reg_0) | 1 |
  653. init_reg.quo_reg_10__and0000(init_reg.quo_reg_10__and00001:O) | NONE(init_reg.quo_reg_10)| 1 |
  654. init_reg.quo_reg_10__or0000(init_reg.quo_reg_10__or00001:O) | NONE(init_reg.quo_reg_10)| 1 |
  655. init_reg.quo_reg_11__and0000(init_reg.quo_reg_11__and00001:O) | NONE(init_reg.quo_reg_11)| 1 |
  656. init_reg.quo_reg_11__or0000(init_reg.quo_reg_11__or00001:O) | NONE(init_reg.quo_reg_11)| 1 |
  657. init_reg.quo_reg_12__and0000(init_reg.quo_reg_12__and00001:O) | NONE(init_reg.quo_reg_12)| 1 |
  658. init_reg.quo_reg_12__or0000(init_reg.quo_reg_12__or00001:O) | NONE(init_reg.quo_reg_12)| 1 |
  659. init_reg.quo_reg_13__and0000(init_reg.quo_reg_13__and00001:O) | NONE(init_reg.quo_reg_13)| 1 |
  660. init_reg.quo_reg_13__or0000(init_reg.quo_reg_13__or00001:O) | NONE(init_reg.quo_reg_13)| 1 |
  661. init_reg.quo_reg_14__and0000(init_reg.quo_reg_14__and00001:O) | NONE(init_reg.quo_reg_14)| 1 |
  662. init_reg.quo_reg_14__or0000(init_reg.quo_reg_14__or00001:O) | NONE(init_reg.quo_reg_14)| 1 |
  663. init_reg.quo_reg_15__and0000(init_reg.quo_reg_15__and00001:O) | NONE(init_reg.quo_reg_15)| 1 |
  664. init_reg.quo_reg_15__or0000(init_reg.quo_reg_15__or00001:O) | NONE(init_reg.quo_reg_15)| 1 |
  665. init_reg.quo_reg_16__and0000(init_reg.quo_reg_16__and00001:O) | NONE(init_reg.quo_reg_16)| 1 |
  666. init_reg.quo_reg_16__or0000(init_reg.quo_reg_16__or00001:O) | NONE(init_reg.quo_reg_16)| 1 |
  667. init_reg.quo_reg_17__and0000(init_reg.quo_reg_17__and00001:O) | NONE(init_reg.quo_reg_17)| 1 |
  668. init_reg.quo_reg_17__or0000(init_reg.quo_reg_17__or00001:O) | NONE(init_reg.quo_reg_17)| 1 |
  669. init_reg.quo_reg_18__and0000(init_reg.quo_reg_18__and00001:O) | NONE(init_reg.quo_reg_18)| 1 |
  670. init_reg.quo_reg_18__or0000(init_reg.quo_reg_18__or00001:O) | NONE(init_reg.quo_reg_18)| 1 |
  671. init_reg.quo_reg_19__and0000(init_reg.quo_reg_19__and00001:O) | NONE(init_reg.quo_reg_19)| 1 |
  672. init_reg.quo_reg_19__or0000(init_reg.quo_reg_19__or00001:O) | NONE(init_reg.quo_reg_19)| 1 |
  673. init_reg.quo_reg_1__and0000(init_reg.quo_reg_1__and00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  674. init_reg.quo_reg_1__or0000(init_reg.quo_reg_1__or00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  675. init_reg.quo_reg_20__and0000(init_reg.quo_reg_20__and00001:O) | NONE(init_reg.quo_reg_20)| 1 |
  676. init_reg.quo_reg_20__or0000(init_reg.quo_reg_20__or00001:O) | NONE(init_reg.quo_reg_20)| 1 |
  677. init_reg.quo_reg_21__and0000(init_reg.quo_reg_21__and00001:O) | NONE(init_reg.quo_reg_21)| 1 |
  678. init_reg.quo_reg_21__or0000(init_reg.quo_reg_21__or00001:O) | NONE(init_reg.quo_reg_21)| 1 |
  679. init_reg.quo_reg_22__and0000(init_reg.quo_reg_22__and00001:O) | NONE(init_reg.quo_reg_22)| 1 |
  680. init_reg.quo_reg_22__or0000(init_reg.quo_reg_22__or00001:O) | NONE(init_reg.quo_reg_22)| 1 |
  681. init_reg.quo_reg_23__and0000(init_reg.quo_reg_23__and00001:O) | NONE(init_reg.quo_reg_23)| 1 |
  682. init_reg.quo_reg_23__or0000(init_reg.quo_reg_23__or00001:O) | NONE(init_reg.quo_reg_23)| 1 |
  683. init_reg.quo_reg_24__and0000(init_reg.quo_reg_24__and00001:O) | NONE(init_reg.quo_reg_24)| 1 |
  684. init_reg.quo_reg_24__or0000(init_reg.quo_reg_24__or00001:O) | NONE(init_reg.quo_reg_24)| 1 |
  685. init_reg.quo_reg_25__and0000(init_reg.quo_reg_25__and00001:O) | NONE(init_reg.quo_reg_25)| 1 |
  686. init_reg.quo_reg_25__or0000(init_reg.quo_reg_25__or00001:O) | NONE(init_reg.quo_reg_25)| 1 |
  687. init_reg.quo_reg_26__and0000(init_reg.quo_reg_26__and00001:O) | NONE(init_reg.quo_reg_26)| 1 |
  688. init_reg.quo_reg_26__or0000(init_reg.quo_reg_26__or0000:O) | NONE(init_reg.quo_reg_26)| 1 |
  689. init_reg.quo_reg_27__and0000(init_reg.quo_reg_27__and00001:O) | NONE(init_reg.quo_reg_27)| 1 |
  690. init_reg.quo_reg_27__or0000(init_reg.quo_reg_27__or00001:O) | NONE(init_reg.quo_reg_27)| 1 |
  691. init_reg.quo_reg_28__and0000(init_reg.quo_reg_28__and00001:O) | NONE(init_reg.quo_reg_28)| 1 |
  692. init_reg.quo_reg_28__or0000(init_reg.quo_reg_28__or00001:O) | NONE(init_reg.quo_reg_28)| 1 |
  693. init_reg.quo_reg_29__and0000(init_reg.quo_reg_29__and00001:O) | NONE(init_reg.quo_reg_29)| 1 |
  694. init_reg.quo_reg_29__or0000(init_reg.quo_reg_29__or00001:O) | NONE(init_reg.quo_reg_29)| 1 |
  695. init_reg.quo_reg_2__and0000(init_reg.quo_reg_2__and00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  696. init_reg.quo_reg_2__or0000(init_reg.quo_reg_2__or00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  697. init_reg.quo_reg_30__and0000(init_reg.quo_reg_30__and00001:O) | NONE(init_reg.quo_reg_30)| 1 |
  698. init_reg.quo_reg_30__or0000(init_reg.quo_reg_30__or00001:O) | NONE(init_reg.quo_reg_30)| 1 |
  699. init_reg.quo_reg_3__and0000(init_reg.quo_reg_3__and00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  700. init_reg.quo_reg_3__or0000(init_reg.quo_reg_3__or00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  701. init_reg.quo_reg_4__and0000(init_reg.quo_reg_4__and00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  702. init_reg.quo_reg_4__or0000(init_reg.quo_reg_4__or00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  703. init_reg.quo_reg_5__and0000(init_reg.quo_reg_5__and00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  704. init_reg.quo_reg_5__or0000(init_reg.quo_reg_5__or00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  705. init_reg.quo_reg_6__and0000(init_reg.quo_reg_6__and00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  706. init_reg.quo_reg_6__or0000(init_reg.quo_reg_6__or00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  707. init_reg.quo_reg_7__and0000(init_reg.quo_reg_7__and00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  708. init_reg.quo_reg_7__or0000(init_reg.quo_reg_7__or00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  709. init_reg.quo_reg_8__and0000(init_reg.quo_reg_8__and00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  710. init_reg.quo_reg_8__or0000(init_reg.quo_reg_8__or00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  711. init_reg.quo_reg_9__and0000(init_reg.quo_reg_9__and00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  712. init_reg.quo_reg_9__or0000(init_reg.quo_reg_9__or00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  713. init_reg.re_reg_10__and0000(init_reg.re_reg_10__and00001:O) | NONE(init_reg.re_reg_10) | 1 |
  714. init_reg.re_reg_10__or0000(init_reg.re_reg_10__or0000:O) | NONE(init_reg.re_reg_10) | 1 |
  715. init_reg.re_reg_11__and0000(init_reg.re_reg_11__and00001:O) | NONE(init_reg.re_reg_11) | 1 |
  716. init_reg.re_reg_11__or0000(init_reg.re_reg_11__or0000:O) | NONE(init_reg.re_reg_11) | 1 |
  717. init_reg.re_reg_12__and0000(init_reg.re_reg_12__and00001:O) | NONE(init_reg.re_reg_12) | 1 |
  718. init_reg.re_reg_12__or0000(init_reg.re_reg_12__or0000:O) | NONE(init_reg.re_reg_12) | 1 |
  719. init_reg.re_reg_13__and0000(init_reg.re_reg_13__and00001:O) | NONE(init_reg.re_reg_13) | 1 |
  720. init_reg.re_reg_13__or0000(init_reg.re_reg_13__or0000_f7:O) | NONE(init_reg.re_reg_13) | 1 |
  721. init_reg.re_reg_14__and0000(init_reg.re_reg_14__and00001:O) | NONE(init_reg.re_reg_14) | 1 |
  722. init_reg.re_reg_14__or0000(init_reg.re_reg_14__or0000:O) | NONE(init_reg.re_reg_14) | 1 |
  723. init_reg.re_reg_15__and0000(init_reg.re_reg_15__and00001:O) | NONE(init_reg.re_reg_15) | 1 |
  724. init_reg.re_reg_15__or0000(init_reg.re_reg_15__or00001:O) | NONE(init_reg.re_reg_15) | 1 |
  725. init_reg.re_reg_16__and0000(init_reg.re_reg_16__and00001:O) | NONE(init_reg.re_reg_16) | 1 |
  726. init_reg.re_reg_16__or0000(init_reg.re_reg_16__or00001:O) | NONE(init_reg.re_reg_16) | 1 |
  727. init_reg.re_reg_17__and0000(init_reg.re_reg_17__and00001:O) | NONE(init_reg.re_reg_17) | 1 |
  728. init_reg.re_reg_17__or0000(init_reg.re_reg_17__or00001:O) | NONE(init_reg.re_reg_17) | 1 |
  729. init_reg.re_reg_18__and0000(init_reg.re_reg_18__and00001:O) | NONE(init_reg.re_reg_18) | 1 |
  730. init_reg.re_reg_18__or0000(init_reg.re_reg_18__or0000:O) | NONE(init_reg.re_reg_18) | 1 |
  731. init_reg.re_reg_19__and0000(init_reg.re_reg_19__and00001:O) | NONE(init_reg.re_reg_19) | 1 |
  732. init_reg.re_reg_19__or0000(init_reg.re_reg_19__or0000:O) | NONE(init_reg.re_reg_19) | 1 |
  733. init_reg.re_reg_1__and0000(init_reg.re_reg_1__and00001:O) | NONE(init_reg.re_reg_1) | 1 |
  734. init_reg.re_reg_1__or0000(init_reg.re_reg_1__or00001:O) | NONE(init_reg.re_reg_1) | 1 |
  735. init_reg.re_reg_20__and0000(init_reg.re_reg_20__and00001:O) | NONE(init_reg.re_reg_20) | 1 |
  736. init_reg.re_reg_20__or0000(init_reg.re_reg_20__or0000:O) | NONE(init_reg.re_reg_20) | 1 |
  737. init_reg.re_reg_21__and0000(init_reg.re_reg_21__and00001:O) | NONE(init_reg.re_reg_21) | 1 |
  738. init_reg.re_reg_21__or0000(init_reg.re_reg_21__or0000:O) | NONE(init_reg.re_reg_21) | 1 |
  739. init_reg.re_reg_22__and0000(init_reg.re_reg_22__and00001:O) | NONE(init_reg.re_reg_22) | 1 |
  740. init_reg.re_reg_22__or0000(init_reg.re_reg_22__or0000:O) | NONE(init_reg.re_reg_22) | 1 |
  741. init_reg.re_reg_23__and0000(init_reg.re_reg_23__and00001:O) | NONE(init_reg.re_reg_23) | 1 |
  742. init_reg.re_reg_23__or0000(init_reg.re_reg_23__or00001:O) | NONE(init_reg.re_reg_23) | 1 |
  743. init_reg.re_reg_24__and0000(init_reg.re_reg_24__and00001:O) | NONE(init_reg.re_reg_24) | 1 |
  744. init_reg.re_reg_24__or0000(init_reg.re_reg_24__or0000:O) | NONE(init_reg.re_reg_24) | 1 |
  745. init_reg.re_reg_25__and0000(init_reg.re_reg_25__and00001:O) | NONE(init_reg.re_reg_25) | 1 |
  746. init_reg.re_reg_25__or0000(init_reg.re_reg_25__or00001:O) | NONE(init_reg.re_reg_25) | 1 |
  747. init_reg.re_reg_26__and0000(init_reg.re_reg_26__and00001:O) | NONE(init_reg.re_reg_26) | 1 |
  748. init_reg.re_reg_26__or0000(init_reg.re_reg_26__or0000:O) | NONE(init_reg.re_reg_26) | 1 |
  749. init_reg.re_reg_27__and0000(init_reg.re_reg_27__and00001:O) | NONE(init_reg.re_reg_27) | 1 |
  750. init_reg.re_reg_27__or0000(init_reg.re_reg_27__or0000:O) | NONE(init_reg.re_reg_27) | 1 |
  751. init_reg.re_reg_28__and0000(init_reg.re_reg_28__and00001:O) | NONE(init_reg.re_reg_28) | 1 |
  752. init_reg.re_reg_28__or0000(init_reg.re_reg_28__or00001:O) | NONE(init_reg.re_reg_28) | 1 |
  753. init_reg.re_reg_29__and0000(init_reg.re_reg_29__and00001:O) | NONE(init_reg.re_reg_29) | 1 |
  754. init_reg.re_reg_29__or0000(init_reg.re_reg_29__or0000:O) | NONE(init_reg.re_reg_29) | 1 |
  755. init_reg.re_reg_2__and0000(init_reg_re_reg_2_mux00311:O) | NONE(init_reg.re_reg_2) | 1 |
  756. init_reg.re_reg_2__or0000(init_reg.re_reg_2__or00001:O) | NONE(init_reg.re_reg_2) | 1 |
  757. init_reg.re_reg_30__and0000(init_reg.re_reg_30__and00001_f7:O)| NONE(init_reg.re_reg_30) | 1 |
  758. init_reg.re_reg_30__or0000(init_reg.re_reg_30__or0000:O) | NONE(init_reg.re_reg_30) | 1 |
  759. init_reg.re_reg_3__and0000(init_reg_re_reg_3_mux00311:O) | NONE(init_reg.re_reg_3) | 1 |
  760. init_reg.re_reg_3__or0000(init_reg.re_reg_3__or00001:O) | NONE(init_reg.re_reg_3) | 1 |
  761. init_reg.re_reg_4__and0000(init_reg.re_reg_4__and00001:O) | NONE(init_reg.re_reg_4) | 1 |
  762. init_reg.re_reg_4__or0000(init_reg.re_reg_4__or00001:O) | NONE(init_reg.re_reg_4) | 1 |
  763. init_reg.re_reg_5__and0000(init_reg_re_reg_5_mux003181_f7:O) | NONE(init_reg.re_reg_5) | 1 |
  764. init_reg.re_reg_5__or0000(init_reg.re_reg_5__or00001:O) | NONE(init_reg.re_reg_5) | 1 |
  765. init_reg.re_reg_6__and0000(init_reg.re_reg_6__and00001:O) | NONE(init_reg.re_reg_6) | 1 |
  766. init_reg.re_reg_6__or0000(init_reg.re_reg_6__or00001:O) | NONE(init_reg.re_reg_6) | 1 |
  767. init_reg.re_reg_7__and0000(init_reg.re_reg_7__and000011:O) | NONE(init_reg.re_reg_7) | 1 |
  768. init_reg.re_reg_7__or0000(init_reg.re_reg_7__or0000:O) | NONE(init_reg.re_reg_7) | 1 |
  769. init_reg.re_reg_8__and0000(init_reg.re_reg_8__and00001:O) | NONE(init_reg.re_reg_8) | 1 |
  770. init_reg.re_reg_8__or0000(init_reg.re_reg_8__or0000:O) | NONE(init_reg.re_reg_8) | 1 |
  771. init_reg.re_reg_9__and0000(init_reg.re_reg_9__and00001:O) | NONE(init_reg.re_reg_9) | 1 |
  772. init_reg.re_reg_9__or0000(init_reg.re_reg_9__or0000:O) | NONE(init_reg.re_reg_9) | 1 |
  773. shift_val_0__or0000(shift_val_0__or00001:O) | NONE(shift_val_0) | 1 |
  774. shift_val_0__or0001(shift_val_0__or00011:O) | NONE(shift_val_0) | 1 |
  775. shift_val_1__and0000(shift_val_1__and00001:O) | NONE(shift_val_1) | 1 |
  776. shift_val_1__or0000(shift_val_1__or00001:O) | NONE(shift_val_1) | 1 |
  777. shift_val_2__and0000(shift_val_2__and00001:O) | NONE(shift_val_2) | 1 |
  778. shift_val_2__or0000(shift_val_2__or00001:O) | NONE(shift_val_2) | 1 |
  779. shift_val_3__and0000(shift_val_3__and00001:O) | NONE(shift_val_3) | 1 |
  780. shift_val_3__or0000(shift_val_3__or00001:O) | NONE(shift_val_3) | 1 |
  781. shift_val_4__and0000(shift_val_4__and00001:O) | NONE(shift_val_4) | 1 |
  782. shift_val_4__or0000(shift_val_4__or00001:O) | NONE(shift_val_4) | 1 |
  783. --------------------------------------------------------------+--------------------------+-------+
  784.  
  785. Timing Summary:
  786. ---------------
  787. Speed Grade: -1
  788.  
  789. Minimum period: 15.087ns (Maximum Frequency: 66.283MHz)
  790. Minimum input arrival time before clock: 10.714ns
  791. Maximum output required time after clock: 12.251ns
  792. Maximum combinational path delay: 16.648ns
  793.  
  794. Timing Detail:
  795. --------------
  796. All values displayed in nanoseconds (ns)
  797.  
  798. =========================================================================
  799. Timing constraint: Default period analysis for Clock 'mclk1'
  800. Clock period: 15.087ns (frequency: 66.283MHz)
  801. Total number of paths / destination ports: 6460283866 / 364
  802. -------------------------------------------------------------------------
  803. Delay: 15.087ns (Levels of Logic = 27)
  804. Source: state_FSM_FFd4 (FF)
  805. Destination: main_reg.quo_reg_31 (FF)
  806. Source Clock: mclk1 rising
  807. Destination Clock: mclk1 rising
  808.  
  809. Data Path: state_FSM_FFd4 to main_reg.quo_reg_31
  810. Gate Net
  811. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  812. ---------------------------------------- ------------
  813. FDR:C->Q 348 0.471 0.666 state_FSM_FFd4 (state_FSM_FFd4)
  814. LUT3:I2->O 9 0.094 0.754 reg_quo_reg<19>1 (reg_quo_reg<19>)
  815. LUT6:I3->O 2 0.094 0.581 tmp_quo_reg_15_mux0000141 (tmp_quo_reg_15_mux0000141)
  816. LUT6:I4->O 1 0.094 0.000 tmp_quo_reg_15_mux0000159_G (N709)
  817. MUXF7:I1->O 1 0.254 0.480 tmp_quo_reg_15_mux0000159 (tmp_quo_reg_15_mux0000159)
  818. LUT6:I5->O 3 0.094 0.347 tmp_quo_reg_15_mux0000201 (tmp_quo_reg_15_mux0000)
  819. DSP48E:B15->PCOUT30 1 3.832 0.000 Mmult_quo_tmp_mult0001 (Mmult_quo_tmp_mult0001_PCOUT_to_Mmult_quo_tmp_mult00011_PCIN_30)
  820. DSP48E:PCIN30->PCOUT47 1 2.013 0.000 Mmult_quo_tmp_mult00011 (Mmult_quo_tmp_mult00011_PCOUT_to_Mmult_quo_tmp_mult00012_PCIN_47)
  821. DSP48E:PCIN47->P0 1 1.816 0.480 Mmult_quo_tmp_mult00012 (quo_tmp_mult0001<17>)
  822. LUT6:I5->O 1 0.094 0.000 Msub_quo_reg_sub_sub0000_lut<17> (Msub_quo_reg_sub_sub0000_lut<17>)
  823. MUXCY:S->O 1 0.372 0.000 Msub_quo_reg_sub_sub0000_cy<17> (Msub_quo_reg_sub_sub0000_cy<17>)
  824. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<18> (Msub_quo_reg_sub_sub0000_cy<18>)
  825. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<19> (Msub_quo_reg_sub_sub0000_cy<19>)
  826. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<20> (Msub_quo_reg_sub_sub0000_cy<20>)
  827. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<21> (Msub_quo_reg_sub_sub0000_cy<21>)
  828. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<22> (Msub_quo_reg_sub_sub0000_cy<22>)
  829. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<23> (Msub_quo_reg_sub_sub0000_cy<23>)
  830. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<24> (Msub_quo_reg_sub_sub0000_cy<24>)
  831. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<25> (Msub_quo_reg_sub_sub0000_cy<25>)
  832. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<26> (Msub_quo_reg_sub_sub0000_cy<26>)
  833. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<27> (Msub_quo_reg_sub_sub0000_cy<27>)
  834. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<28> (Msub_quo_reg_sub_sub0000_cy<28>)
  835. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<29> (Msub_quo_reg_sub_sub0000_cy<29>)
  836. XORCY:CI->O 2 0.357 0.341 Msub_quo_reg_sub_sub0000_xor<30> (quo_reg_sub_sub0000<30>)
  837. INV:I->O 1 0.238 0.000 Madd_main_reg_quo_reg_not0000<30>1_INV_0 (Madd_main_reg_quo_reg_not0000<30>)
  838. MUXCY:S->O 0 0.372 0.000 Madd_main_reg.quo_reg_addsub0000_cy<30> (Madd_main_reg.quo_reg_addsub0000_cy<30>)
  839. XORCY:CI->O 1 0.357 0.480 Madd_main_reg.quo_reg_addsub0000_xor<31> (main_reg_quo_reg_addsub0000<31>)
  840. LUT3:I2->O 1 0.094 0.000 main_reg_quo_reg_mux0000<31>1 (main_reg_quo_reg_mux0000<31>)
  841. FD:D -0.018 main_reg.quo_reg_31
  842. ----------------------------------------
  843. Total 15.087ns (10.958ns logic, 4.129ns route)
  844. (72.6% logic, 27.4% route)
  845.  
  846. =========================================================================
  847. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  848. Total number of paths / destination ports: 7 / 7
  849. -------------------------------------------------------------------------
  850. Offset: 2.334ns (Levels of Logic = 2)
  851. Source: go (PAD)
  852. Destination: i_0 (FF)
  853. Destination Clock: mclk1 rising
  854.  
  855. Data Path: go to i_0
  856. Gate Net
  857. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  858. ---------------------------------------- ------------
  859. IBUF:I->O 3 0.818 0.491 go_IBUF (go_IBUF)
  860. LUT3:I2->O 5 0.094 0.358 i_or00011 (i_or0001)
  861. FDS:S 0.573 i_0
  862. ----------------------------------------
  863. Total 2.334ns (1.485ns logic, 0.849ns route)
  864. (63.6% logic, 36.4% route)
  865.  
  866. =========================================================================
  867. Timing constraint: Default OFFSET IN BEFORE for Clock 'divisor<0>'
  868. Total number of paths / destination ports: 9471 / 98
  869. -------------------------------------------------------------------------
  870. Offset: 10.714ns (Levels of Logic = 14)
  871. Source: divisor<8> (PAD)
  872. Destination: b_n_29 (LATCH)
  873. Destination Clock: divisor<0> falling
  874.  
  875. Data Path: divisor<8> to b_n_29
  876. Gate Net
  877. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  878. ---------------------------------------- ------------
  879. IBUF:I->O 136 0.818 1.216 divisor_8_IBUF (divisor_8_IBUF)
  880. LUT6:I0->O 1 0.094 0.000 b_n_mux0031<29>1112 (b_n_mux0031<29>1112)
  881. MUXF7:I0->O 1 0.251 0.973 b_n_mux0031<29>111_f7 (b_n_mux0031<29>111)
  882. LUT5:I0->O 1 0.094 0.789 b_n_mux0031<29>240_SW0 (N2941)
  883. LUT6:I2->O 1 0.094 0.576 b_n_mux0031<29>240 (b_n_mux0031<29>240)
  884. LUT6:I4->O 1 0.094 0.973 b_n_mux0031<29>312_SW0 (N552)
  885. LUT6:I1->O 1 0.094 0.480 b_n_mux0031<29>312 (b_n_mux0031<29>312)
  886. LUT6:I5->O 1 0.094 0.480 b_n_mux0031<29>368 (b_n_mux0031<29>368)
  887. LUT6:I5->O 1 0.094 0.710 b_n_mux0031<29>448 (b_n_mux0031<29>448)
  888. LUT3:I0->O 1 0.094 0.710 b_n_mux0031<29>521_SW0 (N554)
  889. LUT6:I3->O 1 0.094 0.480 b_n_mux0031<29>521 (b_n_mux0031<29>521)
  890. LUT6:I5->O 1 0.094 0.000 b_n_mux0031<29>643_SW01 (b_n_mux0031<29>643_SW0)
  891. MUXF7:I0->O 1 0.251 0.973 b_n_mux0031<29>643_SW0_f7 (N654)
  892. LUT6:I1->O 3 0.094 0.000 b_n_mux0031<29>643 (b_n_mux0031<29>)
  893. LDCP:D -0.071 b_n_29
  894. ----------------------------------------
  895. Total 10.714ns (2.354ns logic, 8.360ns route)
  896. (22.0% logic, 78.0% route)
  897.  
  898. =========================================================================
  899. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  900. Total number of paths / destination ports: 2656670 / 64
  901. -------------------------------------------------------------------------
  902. Offset: 12.251ns (Levels of Logic = 55)
  903. Source: i_re_1 (FF)
  904. Destination: re<30> (PAD)
  905. Source Clock: mclk1 rising
  906.  
  907. Data Path: i_re_1 to re<30>
  908. Gate Net
  909. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  910. ---------------------------------------- ------------
  911. FD:C->Q 26 0.471 0.915 i_re_1 (i_re_1)
  912. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0013_lutdi (Mcompar_re_cmp_ge0013_lutdi)
  913. MUXCY:DI->O 1 0.362 0.000 Mcompar_re_cmp_ge0013_cy<0> (Mcompar_re_cmp_ge0013_cy<0>)
  914. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<1> (Mcompar_re_cmp_ge0013_cy<1>)
  915. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<2> (Mcompar_re_cmp_ge0013_cy<2>)
  916. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<3> (Mcompar_re_cmp_ge0013_cy<3>)
  917. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<4> (Mcompar_re_cmp_ge0013_cy<4>)
  918. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<5> (Mcompar_re_cmp_ge0013_cy<5>)
  919. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<6> (Mcompar_re_cmp_ge0013_cy<6>)
  920. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<7> (Mcompar_re_cmp_ge0013_cy<7>)
  921. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<8> (Mcompar_re_cmp_ge0013_cy<8>)
  922. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<9> (Mcompar_re_cmp_ge0013_cy<9>)
  923. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<10> (Mcompar_re_cmp_ge0013_cy<10>)
  924. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<11> (Mcompar_re_cmp_ge0013_cy<11>)
  925. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<12> (Mcompar_re_cmp_ge0013_cy<12>)
  926. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<13> (Mcompar_re_cmp_ge0013_cy<13>)
  927. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<14> (Mcompar_re_cmp_ge0013_cy<14>)
  928. MUXCY:CI->O 39 0.254 1.102 Mcompar_re_cmp_ge0013_cy<15> (re_cmp_ge0013)
  929. LUT5:I0->O 1 0.094 0.789 re_mux0000<1>211 (N591)
  930. LUT6:I2->O 1 0.094 0.480 re_mux0000<1>102_SW0 (N296)
  931. LUT6:I5->O 1 0.094 0.576 re_mux0000<1>102 (re_mux0000<1>102)
  932. LUT6:I4->O 1 0.094 0.576 re_mux0000<1>171_SW0 (N298)
  933. LUT5:I3->O 1 0.094 0.576 re_mux0000<1>171 (re_mux0000<1>)
  934. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<1> (Maddsub_re_share0000_lut<1>)
  935. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<1> (Maddsub_re_share0000_cy<1>)
  936. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<2> (Maddsub_re_share0000_cy<2>)
  937. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  938. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  939. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  940. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  941. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  942. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  943. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  944. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  945. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  946. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  947. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  948. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  949. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  950. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  951. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  952. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  953. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  954. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  955. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  956. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  957. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  958. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  959. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  960. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  961. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  962. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  963. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  964. XORCY:CI->O 1 0.357 0.789 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  965. LUT5:I1->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  966. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  967. ----------------------------------------
  968. Total 12.251ns (6.112ns logic, 6.139ns route)
  969. (49.9% logic, 50.1% route)
  970.  
  971. =========================================================================
  972. Timing constraint: Default path analysis
  973. Total number of paths / destination ports: 895370539 / 64
  974. -------------------------------------------------------------------------
  975. Delay: 16.648ns (Levels of Logic = 73)
  976. Source: divisor<2> (PAD)
  977. Destination: re<30> (PAD)
  978.  
  979. Data Path: divisor<2> to re<30>
  980. Gate Net
  981. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  982. ---------------------------------------- ------------
  983. IBUF:I->O 122 0.818 0.720 divisor_2_IBUF (divisor_2_IBUF)
  984. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0011_Madd_lut<2> (Mmult_re_mult0011_Madd_lut<2>)
  985. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0011_Madd_cy<2> (Mmult_re_mult0011_Madd_cy<2>)
  986. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<3> (Mmult_re_mult0011_Madd_cy<3>)
  987. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<4> (Mmult_re_mult0011_Madd_cy<4>)
  988. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<5> (Mmult_re_mult0011_Madd_cy<5>)
  989. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<6> (Mmult_re_mult0011_Madd_cy<6>)
  990. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<7> (Mmult_re_mult0011_Madd_cy<7>)
  991. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<8> (Mmult_re_mult0011_Madd_cy<8>)
  992. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<9> (Mmult_re_mult0011_Madd_cy<9>)
  993. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<10> (Mmult_re_mult0011_Madd_cy<10>)
  994. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<11> (Mmult_re_mult0011_Madd_cy<11>)
  995. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<12> (Mmult_re_mult0011_Madd_cy<12>)
  996. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<13> (Mmult_re_mult0011_Madd_cy<13>)
  997. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<14> (Mmult_re_mult0011_Madd_cy<14>)
  998. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<15> (Mmult_re_mult0011_Madd_cy<15>)
  999. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<16> (Mmult_re_mult0011_Madd_cy<16>)
  1000. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<17> (Mmult_re_mult0011_Madd_cy<17>)
  1001. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<18> (Mmult_re_mult0011_Madd_cy<18>)
  1002. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<19> (Mmult_re_mult0011_Madd_cy<19>)
  1003. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<20> (Mmult_re_mult0011_Madd_cy<20>)
  1004. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<21> (Mmult_re_mult0011_Madd_cy<21>)
  1005. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<22> (Mmult_re_mult0011_Madd_cy<22>)
  1006. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<23> (Mmult_re_mult0011_Madd_cy<23>)
  1007. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<24> (Mmult_re_mult0011_Madd_cy<24>)
  1008. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<25> (Mmult_re_mult0011_Madd_cy<25>)
  1009. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<26> (Mmult_re_mult0011_Madd_cy<26>)
  1010. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<27> (Mmult_re_mult0011_Madd_cy<27>)
  1011. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<28> (Mmult_re_mult0011_Madd_cy<28>)
  1012. XORCY:CI->O 1 0.357 0.576 Mmult_re_mult0011_Madd_xor<29> (Mmult_re_mult0011_Madd_29)
  1013. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0011_Madd1_lut<29> (Mmult_re_mult0011_Madd1_lut<29>)
  1014. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0011_Madd1_cy<29> (Mmult_re_mult0011_Madd1_cy<29>)
  1015. XORCY:CI->O 1 0.357 0.336 Mmult_re_mult0011_Madd1_xor<30> (re_mult0011<30>)
  1016. INV:I->O 1 0.238 0.000 Madd_re_not0004<30>1_INV_0 (Madd_re_not0004<30>)
  1017. MUXCY:S->O 0 0.372 0.000 Madd_re_sub0006_cy<30> (Madd_re_sub0006_cy<30>)
  1018. XORCY:CI->O 2 0.357 0.794 Madd_re_sub0006_xor<31> (re_sub0006<31>)
  1019. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0015_lutdi15 (Mcompar_re_cmp_ge0015_lutdi15)
  1020. MUXCY:DI->O 32 0.590 0.837 Mcompar_re_cmp_ge0015_cy<15> (re_cmp_ge0015)
  1021. LUT5:I2->O 1 0.094 0.973 re_mux0000<3>54_SW0 (N364)
  1022. LUT6:I1->O 1 0.094 0.710 re_mux0000<3>54 (re_mux0000<3>54)
  1023. LUT6:I3->O 1 0.094 0.789 re_mux0000<3>91_SW0 (N6421)
  1024. LUT6:I2->O 1 0.094 0.576 re_mux0000<3>91 (re_mux0000<3>)
  1025. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<3> (Maddsub_re_share0000_lut<3>)
  1026. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  1027. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  1028. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  1029. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  1030. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  1031. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  1032. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  1033. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  1034. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  1035. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  1036. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  1037. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  1038. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  1039. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  1040. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  1041. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  1042. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  1043. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  1044. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  1045. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  1046. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  1047. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  1048. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  1049. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  1050. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  1051. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  1052. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  1053. XORCY:CI->O 1 0.357 0.789 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  1054. LUT5:I1->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  1055. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  1056. ----------------------------------------
  1057. Total 16.648ns (9.212ns logic, 7.436ns route)
  1058. (55.3% logic, 44.7% route)
  1059.  
  1060. =========================================================================
  1061.  
  1062.  
  1063. Total REAL time to Xst completion: 1510.00 secs
  1064. Total CPU time to Xst completion: 1509.37 secs
  1065.  
  1066. -->
  1067.  
  1068.  
  1069. Total memory usage is 813388 kilobytes
  1070.  
  1071. Number of errors : 0 ( 0 filtered)
  1072. Number of warnings : 87 ( 0 filtered)
  1073. Number of infos : 38 ( 0 filtered)
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