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- module JKflipflopTF (
- input J, K,
- input clock,
- output reg [3:0] Q, Qb
- );
- initial Q <= 4'b0;
- // Function to implement JK flip-flop logic
- function [1:0] F (input J, K);
- begin
- case ({J, K})
- 2'b00: F[0] = Q[0]; // Hold state (no change)
- 2'b01: F[0] = 1'b0; // Reset
- 2'b10: F[0] = 1'b1; // Set
- 2'b11: F[0] = !Q[0]; // Toggle
- endcase
- F[1] = !F[0];
- end
- endfunction
- // Counter logic using always block
- always @(posedge clock) begin
- Q[3] <= F(Q[3], !Q[0]); // Update MSB
- Q[2] <= F(Q[2], Q[3]); // Update next based on current MSB
- Q[1] <= F(Q[1], Q[2]);
- Q[0] <= F(Q[0], J); // Update LSB based on J
- Qb <= ~Q; // Assign complement of Q to Qb
- end
- endmodule
- module JKflipflopTFTB;
- reg clock, reset;
- reg J, K;
- wire [3:0] Q, Qb;
- JKflipflopTF counter (
- .J(J),
- .K(K),
- .clock(clock),
- .Q(Q),
- .Qb(Qb)
- );
- // Generate clock signal
- always #10 clock = !clock;
- // Optional reset logic (not used in this example)
- initial begin
- reset = 1'b1;
- #10 reset = 1'b0;
- end
- initial begin
- $monitor("Count = %b", Q);
- clock <= 1'b0;
- J <= 1'b1; // Set J to 1 for increment
- K <= 1'b0; // Set K to 0 to maintain state (previously 1'b1)
- #100;
- end
- always @(posedge clock) begin
- // Removed unnecessary code (previously caused issues)
- $display("Clock cycle: %d, Q: %b, Qb: %b", $time, Q, Qb); // Display values
- end
- endmodule
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