module module_name (<ports declaration>);

// scheduling control unit (may also be an FSM)
localparam CSTEP_NUM = 10;      // number of c-steps in schedule
logic [3:0] cstep_counter;
always @(posedge clk_i)
    begin
    if (rst_i) cstep_counter <= 4’d0;
    else if (cstep_counter == CSTEP_NUM-1) cstep_counter <= 4’d0;
    else cstep_counter <= cstep_counter + 4’d1;
    end
logic computation_finished_o;   // identifies completion of execution
assign computation_finished_o = (cstep_counter == CSTEP_NUM-1) ? 1’b1 : 1’b0;

// datapath
<datapath signals declaration>
always @*
    begin
    <default value assignments>
    case (cstep_counter)
        4’d0: begin some_dst = some_src0 + some_src1; end // stage 0 of execution
        4’d1: begin … end                       // stage 1 of execution
        …
    endcase

endmodule