fsm4_tb

`timescale 1ns / 1ps

module fsm4_tb;

reg clock, rst, enab;
reg [31:0] A_test, B_test;
wire [35:0] res;
reg [35:0] expected_res;

fsm4 func(
    .clk(clock),
    .reset(rst),
    .enable(enab),
    .A(A_test),
    .B(B_test),
    .res(res)
);

integer i;

initial begin
    i = 0;
    clock = 0;
    rst = 0;
    enab = 0;
    A_test = 5;
    B_test = 6;

    expected_res = ((A_test + B_test)*4 + B_test)/2 + (B_test/2 + A_test*4);
    enab = 1;

    for (i = 0; i < 10; i = i + 1) begin
        #5 clock = ~clock;
        $display ("Current state: %d", func.cur_state);
        #5 clock = ~clock;
        $display ("Current state: %d", func.cur_state);
        $display ("sum_1: %d", func.sum_1);
        if(func.cur_state == 8)
            $display ("Module result: %d; expected: %d", res, expected_res);
    end

    $stop;
end
endmodule