/*
 * Finite state machine.
 * If input 'a' is asserted, the state machine
 * moves IDLE->STATE_1->FINAL and remains in FINAL.
 * If 'a' is not asserted, FSM returns to idle.
 * Output 'out1' asserts when state machine is in
 * STATE_1. 'out2' asserts when state machine is in
 * FINAL state.
 */
module fsm (
  input  logic clk ,
  input  logic rst ,
  input  logic a   ,
  output logic out1,
  output logic out2
);

  enum {
    IDLE,    // Waiting for the sun to rise
    STATE_1, // Doing a lot of work here!
    FINAL,   // Whew, done, lets go back to Idle
    XXX      // Trap!
  } state, next;

  // Next state logic
  always @(posedge clk or posedge rst)
    if (rst) state <= IDLE;
    else     state <= next;

  // State transitions and outputs
  always_comb begin
    // Default outputs
    out1 = 0;
    out2 = 0;
    next = XXX;

    case (state)
      IDLE : begin
        if (a) state <= STATE_1;
        else   state <= IDLE; // @loopback
      end

      STATE_1 : begin
        out1 = 1;
        if (a) state <= FINAL;
        else   state <= IDLE;
      end

      FINAL : begin
        out2 = 1;
        if (a) state <= FINAL; // @loopback
        else   state <= IDLE;
      end

      default :
        state <= XXX;
    endcase
  end

endmodule