----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    10:40:06 12/14/2011
-- Design Name:
-- Module Name:    small_ram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity small_ram is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           iRNW : in  STD_LOGIC;
           iADDRESS : in  STD_LOGIC_VECTOR (1 downto 0);
           ioDATA : inout  STD_LOGIC_VECTOR (3 downto 0));
end small_ram;

architecture Behavioral of small_ram is
  signal sR0, sR1, sR2, sR3: std_logic_vector(3 DOWNTO 0);
  signal sWE: std_logic_vector(3 DOWNTO 0);
  signal sOE: std_logic_vector(3 DOWNTO 0);

begin

  -- registri

  process (iCLK) begin
    if (rising_edge(iCLK)) then
      if (inRST = '0') then
        sR0 <= (others => '0');
      elsif (sWE(0) = '1') then
        sR0 <= ioDATA;
      end if;
    end if;
  end process;

  process (iCLK) begin
    if (rising_edge(iCLK)) then
      if (inRST = '0') then
        sR1 <= (others => '0');
      elsif (sWE(1) = '1') then
        sR1 <= ioDATA;
      end if;
    end if;
  end process;

  process (iCLK) begin
    if (rising_edge(iCLK)) then
      if (inRST = '0') then
        sR2 <= (others => '0');
      elsif (sWE(2) = '1') then
        sR2 <= ioDATA;
      end if;
    end if;
  end process;

  process (iCLK) begin
    if (rising_edge(iCLK)) then
      if (inRST = '0') then
        sR3 <= (others => '0');
      elsif (sWE(3) = '1') then
        sR3 <= ioDATA;
      end if;
    end if;
  end process;

  -- dekoderi

  PROCESS(iADDRESS, iRNW) BEGIN
    IF (iRNW = '0') THEN
      CASE iADDRESS IS
        WHEN "00" => sWE <= "0001"; -- upis u R0
        WHEN "01" => sWE <= "0010"; -- upis u R1
        WHEN "10" => sWE <= "0100"; -- upis u R2
        WHEN "11" => sWE <= "1000"; -- upis u R3
        WHEN OTHERS => sWE <= "0000"; -- nema upisa
      END CASE;
    ELSE
      sWE <= "0000"; -- nema upisa
    END IF;
  END PROCESS;

  PROCESS(iADDRESS, iRNW) BEGIN
    IF (iRNW = '1') THEN
      CASE iADDRESS IS
        WHEN "00" => sOE <= "0001"; -- upis u R0
        WHEN "01" => sOE <= "0010"; -- upis u R1
        WHEN "10" => sOE <= "0100"; -- upis u R2
        WHEN "11" => sOE <= "1000"; -- upis u R3
        WHEN OTHERS => sOE <= "0000"; -- nema upisa
      END CASE;
    ELSE
      sOE <= "0000"; -- nema upisa
    END IF;
  END PROCESS;

  -- baferi sa 3 stanja

  ioDATA <= (OTHERS => 'Z') WHEN (sOE(0) = '0') ELSE sR0;
  ioDATA <= (OTHERS => 'Z') WHEN (sOE(1) = '0') ELSE sR1;
  ioDATA <= (OTHERS => 'Z') WHEN (sOE(2) = '0') ELSE sR2;
  ioDATA <= (OTHERS => 'Z') WHEN (sOE(3) = '0') ELSE sR3;


end Behavioral;

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   10:50:39 12/14/2011
-- Design Name:
-- Module Name:   F:/lprs1_aud_vezbe/k2_priprema/base/group2_1/small_ram_tb.vhd
-- Project Name:  group2_1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: small_ram
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY small_ram_tb IS
END small_ram_tb;

ARCHITECTURE behavior OF small_ram_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT small_ram
    PORT(
         iCLK : IN  std_logic;
         inRST : IN  std_logic;
         iRNW : IN  std_logic;
         iADDRESS : IN  std_logic_vector(1 downto 0);
         ioDATA : INOUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;

   --Constants
   constant iCLK_period : time := 10ns;

   --Inputs
   signal iCLK : std_logic := '0';
   signal inRST : std_logic := '0';
   signal iRNW : std_logic := '0';
   signal iADDRESS : std_logic_vector(1 downto 0) := (others => '0');

    --BiDirs
   signal ioDATA : std_logic_vector(3 downto 0);

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: small_ram PORT MAP (
          iCLK => iCLK,
          inRST => inRST,
          iRNW => iRNW,
          iADDRESS => iADDRESS,
          ioDATA => ioDATA
        );


   -- Clock process definitions
   iCLK_process :process
   begin
          iCLK <= '0';
          wait for iCLK_period/2;
          iCLK <= '1';
          wait for iCLK_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin
       -- ciklus 1
      inRST <= '0';
      iRNW <= '0';
      iADDRESS <= std_logic_vector(to_unsigned(0,2));
      ioDATA <= (others => 'Z');
      wait for iCLK_period;

       -- ciklus 2
      inRST <= '1';
      iRNW <= '0';
      iADDRESS <= std_logic_vector(to_unsigned(0,2));
      ioDATA <= x"3"; -- heksadecimalan format
      wait for iCLK_period;

       -- ciklus 3
      inRST <= '1';
      iRNW <= '0';
      iADDRESS <= std_logic_vector(to_unsigned(1,2));
      ioDATA <= x"2";
      wait for iCLK_period;

       -- ciklus 4
      inRST <= '1';
      iRNW <= '0';
      iADDRESS <= std_logic_vector(to_unsigned(2,2));
      ioDATA <= x"1";
      wait for iCLK_period;

       -- ciklus 5
      inRST <= '1';
      iRNW <= '1';
      iADDRESS <= std_logic_vector(to_unsigned(2,2));
      ioDATA <= (others => 'Z');
      wait for iCLK_period;

       -- ciklus 6
      inRST <= '1';
      iRNW <= '1';
      iADDRESS <= std_logic_vector(to_unsigned(1,2));
      ioDATA <= (others => 'Z');
      wait for iCLK_period;

       -- ciklus 7
      inRST <= '1';
      iRNW <= '1';
      iADDRESS <= std_logic_vector(to_unsigned(0,2));
      ioDATA <= (others => 'Z');
      wait for iCLK_period;

      wait;
   end process;

END;