Lab3

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;
use ieee.std_logic_textio.all;

entity autoTestCounter is
--  Port ( );
end autoTestCounter;

architecture Behavioral of autoTestCounter is
    signal OE: std_logic := 'U';
    signal ACLR: std_logic := 'U';
    signal SCLR: std_logic := 'U';
    signal LOAD: std_logic := 'U';
    signal ENP: std_logic := 'U';
    signal ENT: std_logic := 'U';
    signal UD: std_logic := 'U';
    signal CLK: std_logic := 'U';
    signal A: std_logic := 'U';
    signal B: std_logic := 'U';
    signal C: std_logic := 'U';
    signal D: std_logic := 'U';
    signal QA: std_logic := 'U';
    signal QB: std_logic := 'U';
    signal QC: std_logic := 'U';
    signal QD: std_logic := 'U';
    signal RCO: std_logic := 'U';
    signal CCO: std_logic := 'U';

function to_std_logic(H, L: boolean) return std_logic is begin
    if H then
        if L then return 'Z';
        else return 'X';
        end if;
    else
        if L then return '1';
        else return '0';
        end if;
    end if;
end function;

function from_std_logic(sgn: std_logic) return string is
begin
    if (sgn = '0') then
        return "false false";
    elsif (sgn = '1') then
        return "false true";
    elsif (sgn = 'X') then
        return "true false";
    elsif (sgn = 'Z') then
        return "true true";
    else
        return "error error";
    end if;
end function;

begin
    mapping: entity work.binaryCounter(Behavioral)
        port map (
            OE => OE,
            UD => UD,
            CLK => CLK,
            ENT => ENT,
            ENP => ENP,
            SCLR => SCLR,
            LOAD => LOAD,
            ACLR => ACLR,
            A => A,
            B => B,
            C => C,
            D => D,
            CCO => CCO,
            RCO => RCO,
            QA => QA,
            QB => QB,
            QC => QC,
            QD => QD
        );

    process
        file input_file: text;
        file output_file: text;
        variable text_row: line;
        variable out_row: line;
        variable OE_h, ACLR_h, SCLR_h, LOAD_h, ENP_h, ENT_h, UD_h, CLK_h, D3_h, D2_h, D1_h, D0_h, Q3_h, Q2_h, Q1_h, Q0_h, RCO_h, CCO_h: boolean;
        variable OE_l, ACLR_l, SCLR_l, LOAD_l, ENP_l, ENT_l, UD_l, CLK_l, D3_l, D2_l, D1_l, D0_l, Q3_l, Q2_l, Q1_l, Q0_l, RCO_l, CCO_l: boolean;
    begin
        file_open(input_file, "C:\Users\nina\Documents\VII semester\Processors\Lab3\Counter.txt", read_mode);
        file_open(output_file, "C:\Users\nina\Documents\VII semester\Processors\Lab3\OutputCounter.txt", write_mode);

        readline(input_file, text_row);
        writeline(output_file, text_row);

        while not endfile(input_file) loop
            readline(input_file, text_row);

            read(text_row, OE_h);
            read(text_row, OE_l);
            read(text_row, ACLR_h);
            read(text_row, ACLR_l);
            read(text_row, SCLR_h);
            read(text_row, SCLR_l);
            read(text_row, LOAD_h);
            read(text_row, LOAD_l);
            read(text_row, ENP_h);
            read(text_row, ENP_l);
            read(text_row, ENT_h);
            read(text_row, ENT_l);
            read(text_row, UD_h);
            read(text_row, UD_l);
            read(text_row, CLK_h);
            read(text_row, CLK_l);
            read(text_row, D3_h);
            read(text_row, D3_l);
            read(text_row, D2_h);
            read(text_row, D2_l);
            read(text_row, D1_h);
            read(text_row, D1_l);
            read(text_row, D0_h);
            read(text_row, D0_l);

            OE <= to_std_logic(OE_h, OE_l);
            ACLR <= to_std_logic(ACLR_h, ACLR_l);
            SCLR <= to_std_logic(SCLR_h, SCLR_l);
            LOAD <= to_std_logic(LOAD_h, LOAD_l);
            ENP <= to_std_logic(ENP_h, ENP_l);
            ENT <= to_std_logic(ENT_h, ENT_l);
            UD <= to_std_logic(UD_h, UD_l);
            CLK <= to_std_logic(CLK_h, CLK_l);
            A <= to_std_logic(D0_h, D0_l);
            B <= to_std_logic(D1_h, D1_l);
            C <= to_std_logic(D2_h, D2_l);
            D <= to_std_logic(D3_h, D3_l);

            wait for 0.001 ns;

            write(out_row, from_std_logic(OE) & " ");
            write(out_row, from_std_logic(ACLR) & " ");
            write(out_row, from_std_logic(SCLR) & " ");
            write(out_row, from_std_logic(LOAD) & " ");
            write(out_row, from_std_logic(ENP) & " ");
            write(out_row, from_std_logic(ENT) & " ");
            write(out_row, from_std_logic(UD) & " ");
            write(out_row, from_std_logic(CLK) & " ");
            write(out_row, from_std_logic(D) & " ");
            write(out_row, from_std_logic(C) & " ");
            write(out_row, from_std_logic(B) & " ");
            write(out_row, from_std_logic(A) & " ");
            write(out_row, from_std_logic(QD) & " ");
            write(out_row, from_std_logic(QC) & " ");
            write(out_row, from_std_logic(QB) & " ");
            write(out_row, from_std_logic(QA) & " ");
            write(out_row, from_std_logic(RCO) & " ");
            write(out_row, from_std_logic(CCO));

            writeline(output_file, out_row);

            wait for 0.001 ns;
        end loop;

        file_close(input_file);
        file_close(output_file);

        wait;
    end process;

end architecture;