main-fsmCounter

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-- Company:
-- Engineer:
--
-- Create Date:    11:36:07 10/29/2023
-- Design Name:
-- Module Name:    fsmCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsmCounter is
    Port ( clk : in  STD_LOGIC;
           pb1 : in  STD_LOGIC;
           pb2 : in  STD_LOGIC;
           led : out  STD_LOGIC_VECTOR (3 downto 0));
end fsmCounter;

architecture Behavioral of fsmCounter is
    type state_type is (idle, counting, max);
    signal state, next_state : state_type;
    signal r_reg : UNSIGNED(3 downto 0);
    signal r_next : UNSIGNED(3 downto 0);

begin

    -- register and clock
    process(clk, pb2)
    begin

        if(pb2 = '1') then
            state <= idle;
        elsif(clk'event and clk = '1') then
            state <= next_state;
            r_reg <= r_next;
        end if;

    end process;

    -- State logic
    process(state, pb1, pb2)
    begin

        case state is
            when idle =>
                if pb1 = '1' then
                    r_next <= r_reg + 1;
                    next_state <= counting;
                else
                    r_next <= (others => '0');
                    next_state <= idle;
                end if;
            when counting =>
                if pb1 = '1' then
                    r_next <= r_reg + 1;
                    next_state <= counting;
                else
                    r_next <= r_reg;
                end if;
                if r_reg = "1111" then
                    next_state <= max;
                else
                    next_state <= counting;
                end if;
            when max =>
                r_next <= r_reg;
                next_state <= max;
        end case;

    end process;

    -- output
    process(state, r_reg)
    begin

        case state is
            when idle | counting | max =>
                led <= STD_LOGIC_VECTOR(r_reg);
        end case;

    end process;

end Behavioral;