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arter97
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  1. art/.git
  2. diff --git a/compiler/optimizing/intrinsics_arm.cc b/compiler/optimizing/intrinsics_arm.cc
  3. index 0ec0366ed..d08aacae3 100644
  4. --- a/compiler/optimizing/intrinsics_arm.cc
  5. +++ b/compiler/optimizing/intrinsics_arm.cc
  6. @@ -2216,15 +2216,51 @@ void IntrinsicCodeGeneratorARM::VisitDoubleIsInfinite(HInvoke* invoke) {
  7.    __ Lsr(out, out, 5);
  8.  }
  9.  
  10. +void IntrinsicLocationsBuilderARM::VisitMathCeil(HInvoke* invoke) {
  11. +  if (features_.HasARMv8AInstructions()) {
  12. +    CreateFPToFPLocations(arena_, invoke);
  13. +  }
  14. +}
  15. +
  16. +void IntrinsicCodeGeneratorARM::VisitMathCeil(HInvoke* invoke) {
  17. +  ArmAssembler* assembler = GetAssembler();
  18. +  DCHECK(codegen_->GetInstructionSetFeatures().HasARMv8AInstructions());
  19. +  __ vrintdp(FromLowSToD(invoke->GetLocations()->Out().AsFpuRegisterPairLow<SRegister>()),
  20. +             FromLowSToD(invoke->GetLocations()->InAt(0).AsFpuRegisterPairLow<SRegister>()));
  21. +}
  22. +
  23. +void IntrinsicLocationsBuilderARM::VisitMathFloor(HInvoke* invoke) {
  24. +  if (features_.HasARMv8AInstructions()) {
  25. +    CreateFPToFPLocations(arena_, invoke);
  26. +  }
  27. +}
  28. +
  29. +void IntrinsicCodeGeneratorARM::VisitMathFloor(HInvoke* invoke) {
  30. +  ArmAssembler* assembler = GetAssembler();
  31. +  DCHECK(codegen_->GetInstructionSetFeatures().HasARMv8AInstructions());
  32. +  __ vrintdm(FromLowSToD(invoke->GetLocations()->Out().AsFpuRegisterPairLow<SRegister>()),
  33. +             FromLowSToD(invoke->GetLocations()->InAt(0).AsFpuRegisterPairLow<SRegister>()));
  34. +}
  35. +
  36. +void IntrinsicLocationsBuilderARM::VisitMathRint(HInvoke* invoke) {
  37. +  if (features_.HasARMv8AInstructions()) {
  38. +    CreateFPToFPLocations(arena_, invoke);
  39. +  }
  40. +}
  41. +
  42. +void IntrinsicCodeGeneratorARM::VisitMathRint(HInvoke* invoke) {
  43. +  ArmAssembler* assembler = GetAssembler();
  44. +  DCHECK(codegen_->GetInstructionSetFeatures().HasARMv8AInstructions());
  45. +  __ vrintdn(FromLowSToD(invoke->GetLocations()->Out().AsFpuRegisterPairLow<SRegister>()),
  46. +             FromLowSToD(invoke->GetLocations()->InAt(0).AsFpuRegisterPairLow<SRegister>()));
  47. +}
  48. +
  49.  UNIMPLEMENTED_INTRINSIC(ARM, MathMinDoubleDouble)
  50.  UNIMPLEMENTED_INTRINSIC(ARM, MathMinFloatFloat)
  51.  UNIMPLEMENTED_INTRINSIC(ARM, MathMaxDoubleDouble)
  52.  UNIMPLEMENTED_INTRINSIC(ARM, MathMaxFloatFloat)
  53.  UNIMPLEMENTED_INTRINSIC(ARM, MathMinLongLong)
  54.  UNIMPLEMENTED_INTRINSIC(ARM, MathMaxLongLong)
  55. -UNIMPLEMENTED_INTRINSIC(ARM, MathCeil)          // Could be done by changing rounding mode, maybe?
  56. -UNIMPLEMENTED_INTRINSIC(ARM, MathFloor)         // Could be done by changing rounding mode, maybe?
  57. -UNIMPLEMENTED_INTRINSIC(ARM, MathRint)
  58.  UNIMPLEMENTED_INTRINSIC(ARM, MathRoundDouble)   // Could be done by changing rounding mode, maybe?
  59.  UNIMPLEMENTED_INTRINSIC(ARM, MathRoundFloat)    // Could be done by changing rounding mode, maybe?
  60.  UNIMPLEMENTED_INTRINSIC(ARM, UnsafeCASLong)     // High register pressure.
  61. diff --git a/compiler/utils/arm/assembler_arm.cc b/compiler/utils/arm/assembler_arm.cc
  62. index a7f454751..939119538 100644
  63. --- a/compiler/utils/arm/assembler_arm.cc
  64. +++ b/compiler/utils/arm/assembler_arm.cc
  65. @@ -944,5 +944,37 @@ void ArmAssembler::FinalizeTrackedLabels() {
  66.    }
  67.  }
  68.  
  69. +int32_t ArmAssembler::EncodeVRINTr(VRINTRoundingMode rm,
  70. +                                   int output_register_code,
  71. +                                   int input_register_code,
  72. +                                   bool is_64bit) {
  73. +  CHECK_NE(output_register_code, kNoSRegister);
  74. +  CHECK_NE(input_register_code, kNoSRegister);
  75. +  uint32_t D, M;
  76. +  uint32_t Vd, Vm;
  77. +  if (is_64bit) {
  78. +    // Encoded as D:Vd and M:Vm.
  79. +    D = (output_register_code >> 4) & 1;
  80. +    Vd = output_register_code & 0xf;
  81. +    M = (input_register_code >> 4) & 1;
  82. +    Vm = input_register_code & 0xf;
  83. +  } else {
  84. +    // Encoded as Vd:D and Vm:M.
  85. +    D = output_register_code & 1;
  86. +    Vd = (output_register_code >> 1) & 0xf;
  87. +    M = input_register_code & 1;
  88. +    Vm = (input_register_code >> 1) & 0xf;
  89. +  }
  90. +  int32_t encoding = (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
  91. +                     B27 | B26 | B25 | B23 |
  92. +                     B21 | B20 | B19 |
  93. +                     B11 | B9 | B6 |
  94. +                     (rm * B16) |
  95. +                     is_64bit * B8 |
  96. +                     D * B22 | (Vd * B12) |
  97. +                     M * B5 | (Vm * B0);
  98. +  return encoding;
  99. +}
  100. +
  101.  }  // namespace arm
  102.  }  // namespace art
  103. diff --git a/compiler/utils/arm/assembler_arm.h b/compiler/utils/arm/assembler_arm.h
  104. index 91fe0e14c..d602f6e0f 100644
  105. --- a/compiler/utils/arm/assembler_arm.h
  106. +++ b/compiler/utils/arm/assembler_arm.h
  107. @@ -665,6 +665,29 @@ class ArmAssembler : public Assembler {
  108.    virtual void vcvtsu(SRegister sd, SRegister sm, Condition cond = AL) = 0;
  109.    virtual void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL) = 0;
  110.  
  111. +  enum VRINTRoundingMode {
  112. +    kVRINTA = 0,
  113. +    kVRINTN = 1,
  114. +    kVRINTP = 2,
  115. +    kVRINTM = 3,
  116. +  };
  117. +
  118. +  int32_t EncodeVRINTr(VRINTRoundingMode rm,
  119. +                       int output_register_code,
  120. +                       int input_register_code,
  121. +                       bool is_64bit);
  122. +
  123. +  virtual void vrints(VRINTRoundingMode rm, SRegister sd, SRegister sm) = 0;
  124. +  virtual void vrintd(VRINTRoundingMode rm, DRegister dd, DRegister dm) = 0;
  125. +  void vrintsa(SRegister sd, SRegister sm) { vrints(kVRINTA, sd, sm); }
  126. +  void vrintda(DRegister dd, DRegister dm) { vrintd(kVRINTA, dd, dm); }
  127. +  void vrintsn(SRegister sd, SRegister sm) { vrints(kVRINTN, sd, sm); }
  128. +  void vrintdn(DRegister dd, DRegister dm) { vrintd(kVRINTN, dd, dm); }
  129. +  void vrintsp(SRegister sd, SRegister sm) { vrints(kVRINTP, sd, sm); }
  130. +  void vrintdp(DRegister dd, DRegister dm) { vrintd(kVRINTP, dd, dm); }
  131. +  void vrintsm(SRegister sd, SRegister sm) { vrints(kVRINTM, sd, sm); }
  132. +  void vrintdm(DRegister dd, DRegister dm) { vrintd(kVRINTM, dd, dm); }
  133. +
  134.    virtual void vcmps(SRegister sd, SRegister sm, Condition cond = AL) = 0;
  135.    virtual void vcmpd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
  136.    virtual void vcmpsz(SRegister sd, Condition cond = AL) = 0;
  137. diff --git a/compiler/utils/arm/assembler_arm32.cc b/compiler/utils/arm/assembler_arm32.cc
  138. index 2805d8647..cfbec2962 100644
  139. --- a/compiler/utils/arm/assembler_arm32.cc
  140. +++ b/compiler/utils/arm/assembler_arm32.cc
  141. @@ -526,6 +526,16 @@ void Arm32Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) {
  142.  }
  143.  
  144.  
  145. +void Arm32Assembler::vrints(VRINTRoundingMode rm, SRegister sd, SRegister sm) {
  146. +  Emit(EncodeVRINTr(rm, static_cast<int>(sd), static_cast<int>(sm), /* is_64bit */ false));
  147. +}
  148. +
  149. +
  150. +void Arm32Assembler::vrintd(VRINTRoundingMode rm, DRegister dd, DRegister dm) {
  151. +  Emit(EncodeVRINTr(rm, static_cast<int>(dd), static_cast<int>(dm), /* is_64bit */ true));
  152. +}
  153. +
  154. +
  155.  void Arm32Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) {
  156.    EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm);
  157.  }
  158. diff --git a/compiler/utils/arm/assembler_arm32.h b/compiler/utils/arm/assembler_arm32.h
  159. index 63be2e2aa..b8ecfcc7f 100644
  160. --- a/compiler/utils/arm/assembler_arm32.h
  161. +++ b/compiler/utils/arm/assembler_arm32.h
  162. @@ -199,6 +199,9 @@ class Arm32Assembler FINAL : public ArmAssembler {
  163.    void vcvtsu(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
  164.    void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE;
  165.  
  166. +  void vrints(VRINTRoundingMode rm, SRegister sd, SRegister sm) OVERRIDE;
  167. +  void vrintd(VRINTRoundingMode rm, DRegister dd, DRegister dm) OVERRIDE;
  168. +
  169.    void vcmps(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
  170.    void vcmpd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
  171.    void vcmpsz(SRegister sd, Condition cond = AL) OVERRIDE;
  172. diff --git a/compiler/utils/arm/assembler_thumb2.cc b/compiler/utils/arm/assembler_thumb2.cc
  173. index bd5875f08..b3c1d9fc0 100644
  174. --- a/compiler/utils/arm/assembler_thumb2.cc
  175. +++ b/compiler/utils/arm/assembler_thumb2.cc
  176. @@ -1114,6 +1114,18 @@ void Thumb2Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) {
  177.  }
  178.  
  179.  
  180. +void Thumb2Assembler::vrints(VRINTRoundingMode rm, SRegister sd, SRegister sm) {
  181. +  CheckCondition(AL);  // VRINT instructions are unpredictable in IT blocks.
  182. +  Emit32(EncodeVRINTr(rm, static_cast<int>(sd), static_cast<int>(sm), /* is_64bit */ false));
  183. +}
  184. +
  185. +
  186. +void Thumb2Assembler::vrintd(VRINTRoundingMode rm, DRegister dd, DRegister dm) {
  187. +  CheckCondition(AL);  // VRINT instructions are unpredictable in IT blocks.
  188. +  Emit32(EncodeVRINTr(rm, static_cast<int>(dd), static_cast<int>(dm), /* is_64bit */ true));
  189. +}
  190. +
  191. +
  192.  void Thumb2Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) {
  193.    EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm);
  194.  }
  195. diff --git a/compiler/utils/arm/assembler_thumb2.h b/compiler/utils/arm/assembler_thumb2.h
  196. index 47a55ebfa..8d012dcd0 100644
  197. --- a/compiler/utils/arm/assembler_thumb2.h
  198. +++ b/compiler/utils/arm/assembler_thumb2.h
  199. @@ -245,6 +245,9 @@ class Thumb2Assembler FINAL : public ArmAssembler {
  200.    void vcvtsu(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
  201.    void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE;
  202.  
  203. +  void vrints(VRINTRoundingMode rm, SRegister sd, SRegister sm) OVERRIDE;
  204. +  void vrintd(VRINTRoundingMode rm, DRegister dd, DRegister dm) OVERRIDE;
  205. +
  206.    void vcmps(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
  207.    void vcmpd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
  208.    void vcmpsz(SRegister sd, Condition cond = AL) OVERRIDE;
  209. diff --git a/disassembler/disassembler_arm.cc b/disassembler/disassembler_arm.cc
  210. index ee4953f8e..be3d7a94d 100644
  211. --- a/disassembler/disassembler_arm.cc
  212. +++ b/disassembler/disassembler_arm.cc
  213. @@ -1481,6 +1481,32 @@ size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr)
  214.            }
  215.            break;
  216.          }
  217. +      case 0x6B:    // 1101011
  218. +      case 0x6F: {  // 1101111
  219. +        constexpr uint32_t fixed_bits_mask   = 0xFFBC0ED0;
  220. +        constexpr uint32_t vrintr_fixed_bits = 0xFEB80A40;
  221. +        if ((instr & fixed_bits_mask) == vrintr_fixed_bits) {
  222. +          opcode << "vrint";
  223. +          int rounding_mode = instr >> 16 & 0x3;
  224. +          switch (rounding_mode) {
  225. +            case 0: opcode << "a"; break;
  226. +            case 1: opcode << "n"; break;
  227. +            case 2: opcode << "p"; break;
  228. +            case 3: opcode << "m"; break;
  229. +            default:
  230. +              LOG(FATAL) << "Unexpected rounding mode " << rounding_mode;
  231. +              UNREACHABLE();
  232. +          }
  233. +          bool double_precision = instr >> 8 & 0x1;
  234. +          if (double_precision) {
  235. +            opcode << ".f64.f64 ";
  236. +          } else {
  237. +            opcode << ".f32.f32 ";
  238. +          }
  239. +          opcode << FpRegister(instr, 12, 22) << ", " << FpRegister(instr, 0, 5);
  240. +        }
  241. +        FALLTHROUGH_INTENDED;
  242. +      }
  243.          case 0x7B: case 0x7F: {
  244.            FpRegister d(instr, 12, 22);
  245.            FpRegister m(instr, 0, 5);
  246. diff --git a/runtime/Android.mk b/runtime/Android.mk
  247. index a4b1a3cb5..3bc025966 100644
  248. --- a/runtime/Android.mk
  249. +++ b/runtime/Android.mk
  250. @@ -582,11 +582,6 @@ endif
  251.    LOCAL_NATIVE_COVERAGE := $(ART_COVERAGE)
  252.  
  253.    ifeq ($$(art_target_or_host),target)
  254. -    ifneq ($$(art_ndebug_or_debug),debug)
  255. -      # Leave the symbols in the shared library so that stack unwinders can
  256. -      # produce meaningful name resolution.
  257. -      LOCAL_STRIP_MODULE := keep_symbols
  258. -    endif
  259.      include $$(BUILD_SHARED_LIBRARY)
  260.    else # host
  261.      ifeq ($$(art_static_or_shared),static)
  262. diff --git a/runtime/arch/arm/instruction_set_features_arm.cc b/runtime/arch/arm/instruction_set_features_arm.cc
  263. index 2aa4ee21d..01faf5cd5 100644
  264. --- a/runtime/arch/arm/instruction_set_features_arm.cc
  265. +++ b/runtime/arch/arm/instruction_set_features_arm.cc
  266. @@ -29,6 +29,7 @@
  267.  
  268.  #if defined(__arm__)
  269.  extern "C" bool artCheckForArmSdivInstruction();
  270. +extern "C" bool artCheckForArmv8AInstructions();
  271.  #endif
  272.  
  273.  namespace art {
  274. @@ -39,23 +40,28 @@ const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromVariant(
  275.    // TODO: set the SMP support based on variant.
  276.    const bool smp = true;
  277.  
  278. -  // Look for variants that have divide support.
  279. -  static const char* arm_variants_with_div[] = {
  280. -          "cortex-a7", "cortex-a12", "cortex-a15", "cortex-a17", "cortex-a53", "cortex-a57",
  281. -          "cortex-a53.a57", "cortex-m3", "cortex-m4", "cortex-r4", "cortex-r5",
  282. -          "cyclone", "denver", "krait", "kryo", "swift" };
  283. +  static const char* arm_variants_with_armv8a[] =
  284. +  { "cortex-a53", "cortex-a57", "cortex-a35", "cortex-a72", "cortex-a53.a57", "cyclone", "denver", "kryo" };
  285. +  bool has_armv8a =
  286. +      FindVariantInArray(arm_variants_with_armv8a, arraysize(arm_variants_with_armv8a), variant);
  287.  
  288. -  bool has_div = FindVariantInArray(arm_variants_with_div, arraysize(arm_variants_with_div),
  289. -                                    variant);
  290. +  // SDIV is always available on ARMv8-A. Look for divide support in other variants.
  291. +  static const char* non_armv8_variants_with_div[] = {
  292. +          "cortex-a7", "cortex-a12", "cortex-a15", "cortex-a17",  "krait", "swift" };
  293.  
  294. -  // Look for variants that have LPAE support.
  295. -  static const char* arm_variants_with_lpae[] = {
  296. -      "cortex-a7", "cortex-a15", "krait", "kryo", "denver", "cortex-a53", "cortex-a57", "cortex-a53.a57"
  297. -  };
  298. -  bool has_lpae = FindVariantInArray(arm_variants_with_lpae, arraysize(arm_variants_with_lpae),
  299. -                                     variant);
  300. +  bool has_div = has_armv8a || FindVariantInArray(non_armv8_variants_with_div,
  301. +                                                  arraysize(non_armv8_variants_with_div),
  302. +                                                  variant);
  303.  
  304. -  if (has_div == false && has_lpae == false) {
  305. +  // ARMv8-A CPUs that support 32bit have atomic 64bit accesses.
  306. +  // Look for other variants that have LPAE support. LPAE support implies atomic LDRD/STRD.
  307. +  static const char* non_armv8_variants_with_lpae[] = { "cortex-a7", "cortex-a15", "krait" };
  308. +  bool has_atomic_ldrd_strd =
  309. +      has_armv8a || FindVariantInArray(non_armv8_variants_with_lpae,
  310. +                                       arraysize(non_armv8_variants_with_lpae),
  311. +                                       variant);
  312. +
  313. +  if (has_div == false && has_atomic_ldrd_strd == false) {
  314.      // Avoid unsupported variants.
  315.      static const char* unsupported_arm_variants[] = {
  316.          // ARM processors that aren't ARMv7 compatible aren't supported.
  317. @@ -97,37 +103,47 @@ const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromVariant(
  318.            << ") using conservative defaults";
  319.      }
  320.    }
  321. -  return new ArmInstructionSetFeatures(smp, has_div, has_lpae);
  322. +
  323. +  return new ArmInstructionSetFeatures(smp, has_div, has_atomic_ldrd_strd, has_armv8a);
  324.  }
  325.  
  326.  const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromBitmap(uint32_t bitmap) {
  327.    bool smp = (bitmap & kSmpBitfield) != 0;
  328.    bool has_div = (bitmap & kDivBitfield) != 0;
  329.    bool has_atomic_ldrd_strd = (bitmap & kAtomicLdrdStrdBitfield) != 0;
  330. -  return new ArmInstructionSetFeatures(smp, has_div, has_atomic_ldrd_strd);
  331. +  bool has_armv8a = (bitmap & kARMv8A) != 0;
  332. +  return new ArmInstructionSetFeatures(smp, has_div, has_atomic_ldrd_strd, has_armv8a);
  333.  }
  334.  
  335.  const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromCppDefines() {
  336.    const bool smp = true;
  337. -#if defined(__ARM_ARCH_EXT_IDIV__)
  338. +#if defined(__ARM_ARCH_8A__)
  339. +  const bool has_armv8a = true;
  340. +#else
  341. +  const bool has_armv8a = false;
  342. +#endif
  343. +  // SDIV is always available on ARMv8-A.
  344. +#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_EXT_IDIV__)
  345.    const bool has_div = true;
  346.  #else
  347.    const bool has_div = false;
  348.  #endif
  349. -#if defined(__ARM_FEATURE_LPAE)
  350. -  const bool has_lpae = true;
  351. +#if defined(__ARM_ARCH_8A__) || defined(__ARM_FEATURE_LPAE)
  352. +  // ARMv8-A implies atomic 64bit accesses.
  353. +  const bool has_atomic_ldrd_strd = true;
  354.  #else
  355. -  const bool has_lpae = false;
  356. +  const bool has_atomic_ldrd_strd = false;
  357.  #endif
  358. -  return new ArmInstructionSetFeatures(smp, has_div, has_lpae);
  359. +  return new ArmInstructionSetFeatures(smp, has_div, has_atomic_ldrd_strd, has_armv8a);
  360.  }
  361.  
  362.  const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromCpuInfo() {
  363.    // Look in /proc/cpuinfo for features we need.  Only use this when we can guarantee that
  364.    // the kernel puts the appropriate feature flags in here.  Sometimes it doesn't.
  365.    bool smp = false;
  366. -  bool has_lpae = false;
  367. +  bool has_atomic_ldrd_strd = false;
  368.    bool has_div = false;
  369. +  bool has_armv8a = false;
  370.  
  371.    std::ifstream in("/proc/cpuinfo");
  372.    if (!in.fail()) {
  373. @@ -145,11 +161,20 @@ const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromCpuInfo() {
  374.              has_div = true;
  375.            }
  376.            if (line.find("lpae") != std::string::npos) {
  377. -            has_lpae = true;
  378. +            has_atomic_ldrd_strd = true;
  379.            }
  380.          } else if (line.find("processor") != std::string::npos &&
  381.              line.find(": 1") != std::string::npos) {
  382.            smp = true;
  383. +        } else if (line.find("architecture") != std::string::npos &&
  384. +                   line.find(": 8") != std::string::npos) {
  385. +          LOG(INFO) << "found architecture ARMv8";
  386. +          // Android is only run on A cores, so ARMv8 implies ARMv8-A.
  387. +          has_armv8a = true;
  388. +          // SDIV is always available on ARMv8-A.
  389. +          has_div = true;
  390. +          // ARMv8-A CPUs that support 32bit have atomic 64bit accesses.
  391. +          has_atomic_ldrd_strd = true;
  392.          }
  393.        }
  394.      }
  395. @@ -157,16 +182,25 @@ const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromCpuInfo() {
  396.    } else {
  397.      LOG(ERROR) << "Failed to open /proc/cpuinfo";
  398.    }
  399. -  return new ArmInstructionSetFeatures(smp, has_div, has_lpae);
  400. +
  401. +  return new ArmInstructionSetFeatures(smp, has_div, has_atomic_ldrd_strd, has_armv8a);
  402.  }
  403.  
  404.  const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromHwcap() {
  405.    bool smp = sysconf(_SC_NPROCESSORS_CONF) > 1;
  406.  
  407.    bool has_div = false;
  408. -  bool has_lpae = false;
  409. +  bool has_atomic_ldrd_strd = false;
  410. +  bool has_armv8a = false;
  411.  
  412.  #if defined(__ANDROID__) && defined(__arm__)
  413. +#if (__ARM_FP & 0x8)
  414. +  has_armv8a = true;
  415. +  // SDIV is always available on ARMv8-A.
  416. +  has_div = true;
  417. +  // ARMv8-A CPUs that support 32bit have atomic 64bit accesses.
  418. +  has_atomic_ldrd_strd = true;
  419. +#elif defined(__arm__)
  420.    uint64_t hwcaps = getauxval(AT_HWCAP);
  421.    LOG(INFO) << "hwcaps=" << hwcaps;
  422.    if ((hwcaps & HWCAP_IDIVT) != 0) {
  423. @@ -176,18 +210,19 @@ const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromHwcap() {
  424.      has_div = true;
  425.    }
  426.    if ((hwcaps & HWCAP_LPAE) != 0) {
  427. -    has_lpae = true;
  428. +    has_atomic_ldrd_strd = true;
  429.    }
  430.  #endif
  431. +#endif
  432.  
  433. -  return new ArmInstructionSetFeatures(smp, has_div, has_lpae);
  434. +  return new ArmInstructionSetFeatures(smp, has_div, has_atomic_ldrd_strd, has_armv8a);
  435.  }
  436.  
  437.  // A signal handler called by a fault for an illegal instruction.  We record the fact in r0
  438.  // and then increment the PC in the signal context to return to the next instruction.  We know the
  439.  // instruction is an sdiv (4 bytes long).
  440. -static void bad_divide_inst_handle(int signo ATTRIBUTE_UNUSED, siginfo_t* si ATTRIBUTE_UNUSED,
  441. -                                   void* data) {
  442. +static void bad_inst_handle(int signo ATTRIBUTE_UNUSED, siginfo_t* si ATTRIBUTE_UNUSED,
  443. +                            void* data) {
  444.  #if defined(__arm__)
  445.    struct ucontext *uc = (struct ucontext *)data;
  446.    struct sigcontext *sc = &uc->uc_mcontext;
  447. @@ -201,18 +236,22 @@ static void bad_divide_inst_handle(int signo ATTRIBUTE_UNUSED, siginfo_t* si ATT
  448.  const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromAssembly() {
  449.    const bool smp = true;
  450.  
  451. -  // See if have a sdiv instruction.  Register a signal handler and try to execute an sdiv
  452. -  // instruction.  If we get a SIGILL then it's not supported.
  453. +  // See if SDIV and ARMv8-A instructions are available. Register a signal handler and
  454. +  // try to execute an sdiv instruction. If we get a SIGILL then it's not supported.
  455.    struct sigaction sa, osa;
  456.    sa.sa_flags = SA_ONSTACK | SA_RESTART | SA_SIGINFO;
  457. -  sa.sa_sigaction = bad_divide_inst_handle;
  458. +  sa.sa_sigaction = bad_inst_handle;
  459.    sigaction(SIGILL, &sa, &osa);
  460.  
  461.    bool has_div = false;
  462. +  bool has_armv8a = false;
  463.  #if defined(__arm__)
  464.    if (artCheckForArmSdivInstruction()) {
  465.      has_div = true;
  466.    }
  467. +  if (artCheckForArmv8AInstructions()) {
  468. +    has_armv8a = true;
  469. +  }
  470.  #endif
  471.  
  472.    // Restore the signal handler.
  473. @@ -225,7 +264,7 @@ const ArmInstructionSetFeatures* ArmInstructionSetFeatures::FromAssembly() {
  474.  #else
  475.    const bool has_lpae = false;
  476.  #endif
  477. -  return new ArmInstructionSetFeatures(smp, has_div, has_lpae);
  478. +  return new ArmInstructionSetFeatures(smp, has_div, has_lpae, has_armv8a);
  479.  }
  480.  
  481.  bool ArmInstructionSetFeatures::Equals(const InstructionSetFeatures* other) const {
  482. @@ -235,13 +274,15 @@ bool ArmInstructionSetFeatures::Equals(const InstructionSetFeatures* other) cons
  483.    const ArmInstructionSetFeatures* other_as_arm = other->AsArmInstructionSetFeatures();
  484.    return IsSmp() == other_as_arm->IsSmp() &&
  485.        has_div_ == other_as_arm->has_div_ &&
  486. -      has_atomic_ldrd_strd_ == other_as_arm->has_atomic_ldrd_strd_;
  487. +      has_atomic_ldrd_strd_ == other_as_arm->has_atomic_ldrd_strd_ &&
  488. +      has_armv8a_ == other_as_arm->has_armv8a_;
  489.  }
  490.  
  491.  uint32_t ArmInstructionSetFeatures::AsBitmap() const {
  492.    return (IsSmp() ? kSmpBitfield : 0) |
  493.        (has_div_ ? kDivBitfield : 0) |
  494. -      (has_atomic_ldrd_strd_ ? kAtomicLdrdStrdBitfield : 0);
  495. +      (has_atomic_ldrd_strd_ ? kAtomicLdrdStrdBitfield : 0) |
  496. +      (has_armv8a_ ? kARMv8A : 0);
  497.  }
  498.  
  499.  std::string ArmInstructionSetFeatures::GetFeatureString() const {
  500. @@ -261,6 +302,11 @@ std::string ArmInstructionSetFeatures::GetFeatureString() const {
  501.    } else {
  502.      result += ",-atomic_ldrd_strd";
  503.    }
  504. +  if (has_armv8a_) {
  505. +    result += ",armv8a";
  506. +  } else {
  507. +    result += ",-armv8a";
  508. +  }
  509.    return result;
  510.  }
  511.  
  512. @@ -268,6 +314,7 @@ const InstructionSetFeatures* ArmInstructionSetFeatures::AddFeaturesFromSplitStr
  513.      const bool smp, const std::vector<std::string>& features, std::string* error_msg) const {
  514.    bool has_atomic_ldrd_strd = has_atomic_ldrd_strd_;
  515.    bool has_div = has_div_;
  516. +  bool has_armv8a = has_armv8a_;
  517.    for (auto i = features.begin(); i != features.end(); i++) {
  518.      std::string feature = Trim(*i);
  519.      if (feature == "div") {
  520. @@ -278,12 +325,16 @@ const InstructionSetFeatures* ArmInstructionSetFeatures::AddFeaturesFromSplitStr
  521.        has_atomic_ldrd_strd = true;
  522.      } else if (feature == "-atomic_ldrd_strd") {
  523.        has_atomic_ldrd_strd = false;
  524. +    } else if (feature == "armv8a") {
  525. +      has_armv8a = true;
  526. +    } else if (feature == "-armv8a") {
  527. +      has_armv8a = false;
  528.      } else {
  529.        *error_msg = StringPrintf("Unknown instruction set feature: '%s'", feature.c_str());
  530.        return nullptr;
  531.      }
  532.    }
  533. -  return new ArmInstructionSetFeatures(smp, has_div, has_atomic_ldrd_strd);
  534. +  return new ArmInstructionSetFeatures(smp, has_div, has_atomic_ldrd_strd, has_armv8a);
  535.  }
  536.  
  537.  }  // namespace art
  538. diff --git a/runtime/arch/arm/instruction_set_features_arm.h b/runtime/arch/arm/instruction_set_features_arm.h
  539. index 221bf1fbc..61f7d0b6a 100644
  540. --- a/runtime/arch/arm/instruction_set_features_arm.h
  541. +++ b/runtime/arch/arm/instruction_set_features_arm.h
  542. @@ -67,6 +67,11 @@ class ArmInstructionSetFeatures FINAL : public InstructionSetFeatures {
  543.      return has_atomic_ldrd_strd_;
  544.    }
  545.  
  546. +  // Are ARMv8-A instructions available?
  547. +  bool HasARMv8AInstructions() const {
  548. +    return has_armv8a_;
  549. +  }
  550. +
  551.    virtual ~ArmInstructionSetFeatures() {}
  552.  
  553.   protected:
  554. @@ -76,20 +81,28 @@ class ArmInstructionSetFeatures FINAL : public InstructionSetFeatures {
  555.                                   std::string* error_msg) const OVERRIDE;
  556.  
  557.   private:
  558. -  ArmInstructionSetFeatures(bool smp, bool has_div, bool has_atomic_ldrd_strd)
  559. +  ArmInstructionSetFeatures(bool smp,
  560. +                            bool has_div,
  561. +                            bool has_atomic_ldrd_strd,
  562. +                            bool has_armv8a)
  563.        : InstructionSetFeatures(smp),
  564. -        has_div_(has_div), has_atomic_ldrd_strd_(has_atomic_ldrd_strd) {
  565. -  }
  566. +        has_div_(has_div),
  567. +        has_atomic_ldrd_strd_(has_atomic_ldrd_strd),
  568. +        has_armv8a_(has_armv8a) {}
  569.  
  570.    // Bitmap positions for encoding features as a bitmap.
  571.    enum {
  572. -    kSmpBitfield = 1,
  573. -    kDivBitfield = 2,
  574. -    kAtomicLdrdStrdBitfield = 4,
  575. +    kSmpBitfield = 1 << 0,
  576. +    kDivBitfield = 1 << 1,
  577. +    kAtomicLdrdStrdBitfield = 1 << 2,
  578. +    kARMv8A = 1 << 3
  579.    };
  580.  
  581.    const bool has_div_;
  582.    const bool has_atomic_ldrd_strd_;
  583. +  // TODO: Eventually we may want a finer grain description, keeping track of the architecture
  584. +  // version and variant. For now this is enough for our purpose.
  585. +  const bool has_armv8a_;
  586.  
  587.    DISALLOW_COPY_AND_ASSIGN(ArmInstructionSetFeatures);
  588.  };
  589. diff --git a/runtime/arch/arm/instruction_set_features_assembly_tests.S b/runtime/arch/arm/instruction_set_features_assembly_tests.S
  590. index c1086df0f..4178ef6f0 100644
  591. --- a/runtime/arch/arm/instruction_set_features_assembly_tests.S
  592. +++ b/runtime/arch/arm/instruction_set_features_assembly_tests.S
  593. @@ -17,22 +17,39 @@
  594.  #include "asm_support_arm.S"
  595.  
  596.  .section .text
  597. -// This function is used to check for the CPU's support for the sdiv
  598. -// instruction at runtime.  It will either return the value 1 or
  599. -// will cause an invalid instruction trap (SIGILL signal).  The
  600. -// caller must arrange for the signal handler to set the r0
  601. -// register to 0 and move the pc forward by 4 bytes (to skip
  602. -// the invalid instruction).
  603. +// These functions are used to check for the CPU's support for the sdiv and
  604. +// ARMv8-A instructions at runtime. They will either return the value 1 or will
  605. +// cause an invalid instruction trap (SIGILL signal).  The caller must arrange
  606. +// for the signal handler to set the r0 register to 0 and move the pc forward by
  607. +// 4 bytes (to skip the invalid instruction).
  608. +
  609.  ENTRY artCheckForArmSdivInstruction
  610.    mov r1,#1
  611. -  // depending on the architecture, the assembler will not allow an
  612. +  // Depending on the architecture, the assembler will not allow an
  613.    // sdiv instruction, so we will have to output the bytes directly.
  614.  
  615. -  // sdiv r0,r1,r1 is two words: 0xfb91 0xf1f0.  We need little endian.
  616. -  .byte 0x91,0xfb,0xf1,0xf0
  617. +  // The T32 encoding for sdiv r0,r1,r1 is two 16bit words: 0xfb91 0xf0f1, with little endianness.
  618. +  .byte 0x91,0xfb
  619. +  .byte 0xf1,0xf0
  620.  
  621. -  // if the divide worked, r0 will have the value #1 (result of sdiv).
  622. +  // If the divide worked, r0 will have the value #1 (result of sdiv).
  623.    // It will have 0 otherwise (set by the signal handler)
  624.    // the value is just returned from this function.
  625.    bx lr
  626.  END artCheckForArmSdivInstruction
  627. +
  628. +ENTRY artCheckForArmv8AInstructions
  629. +  // Depending on the architecture, the assembler will not allow a
  630. +  // `vrint` instruction, so we will have to output the bytes directly.
  631. +
  632. +  // Move `true` into thre result register. The signal handler will set it to 0
  633. +  // if execution of the instruction below fails
  634. +  mov r0,#1
  635. +
  636. +  // The T32 encoding for vrinta.f32.f32 s0,s0 is two 16bit words: 0xfeb8,0x0a40, with little
  637. +  // endianness.
  638. +  .byte 0xb8,0xfe
  639. +  .byte 0x40,0x0a
  640. +
  641. +  bx lr
  642. +END artCheckForArmv8AInstructions
  643.  
  644. bionic/.git
  645. diff --git a/libc/Android.mk b/libc/Android.mk
  646. index 693f0a2a6..edb4b5205 100644
  647. --- a/libc/Android.mk
  648. +++ b/libc/Android.mk
  649. @@ -1409,10 +1409,6 @@ LOCAL_ADDITIONAL_DEPENDENCIES := \
  650.      $(LOCAL_PATH)/libc.mips.brillo.map \
  651.      $(LOCAL_PATH)/libc.x86.brillo.map \
  652.  
  653. -# Leave the symbols in the shared library so that stack unwinders can produce
  654. -# meaningful name resolution.
  655. -LOCAL_STRIP_MODULE := keep_symbols
  656. -
  657.  # Do not pack libc.so relocations; see http://b/20645321 for details.
  658.  LOCAL_PACK_MODULE_RELOCATIONS := false
  659.  
  660. diff --git a/libc/arch-arm/cortex-a15/bionic/strlen.S b/libc/arch-arm/cortex-a15/bionic/strlen.S
  661. index 121d9aca6..4d4ba35f7 100644
  662. --- a/libc/arch-arm/cortex-a15/bionic/strlen.S
  663. +++ b/libc/arch-arm/cortex-a15/bionic/strlen.S
  664. @@ -1,91 +1,145 @@
  665. +/* Copyright (c) 2010-2011,2013 Linaro Limited
  666. +   All rights reserved.
  667. +
  668. +   Redistribution and use in source and binary forms, with or without
  669. +   modification, are permitted provided that the following conditions
  670. +   are met:
  671. +
  672. +      * Redistributions of source code must retain the above copyright
  673. +      notice, this list of conditions and the following disclaimer.
  674. +
  675. +      * Redistributions in binary form must reproduce the above copyright
  676. +      notice, this list of conditions and the following disclaimer in the
  677. +      documentation and/or other materials provided with the distribution.
  678. +
  679. +      * Neither the name of Linaro Limited nor the names of its
  680. +      contributors may be used to endorse or promote products derived
  681. +      from this software without specific prior written permission.
  682. +
  683. +   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  684. +   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  685. +   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  686. +   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  687. +   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  688. +   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  689. +   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  690. +   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  691. +   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  692. +   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  693. +   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  694. + */
  695. +
  696.  /*
  697. - * Copyright (c) 2011 Apple, Inc. All rights reserved.
  698. - *
  699. - * @APPLE_LICENSE_HEADER_START@
  700. - *
  701. - * This file contains Original Code and/or Modifications of Original Code
  702. - * as defined in and that are subject to the Apple Public Source License
  703. - * Version 2.0 (the 'License'). You may not use this file except in
  704. - * compliance with the License. Please obtain a copy of the License at
  705. - * http://www.opensource.apple.com/apsl/ and read it before using this
  706. - * file.
  707. - *
  708. - * The Original Code and all software distributed under the License are
  709. - * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  710. - * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  711. - * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  712. - * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  713. - * Please see the License for the specific language governing rights and
  714. - * limitations under the License.
  715. - *
  716. - * @APPLE_LICENSE_HEADER_END@
  717. +   Assumes:
  718. +   ARMv6T2, AArch32
  719. +
  720. +   Adapted to Bionic by Bernhard Rosenkränzer <bero@linaro.org>
  721.   */
  722.  
  723.  #include <private/bionic_asm.h>
  724.  
  725. -.syntax unified
  726. -.code 32
  727. -
  728. -#define addr r0
  729. -#define word r1
  730. -#define temp r2
  731. -#define mask r3
  732. -#define save ip
  733. -#define indx r0
  734. -
  735. -.macro IfWordDoesntContainNUL_SetZ
  736. -//  In each word of the string, we check for NUL bytes via a saturating
  737. -//  unsigned subtraction of each byte from 0x1.  The result of this is
  738. -//  non-zero if and only if the corresponding byte in the string is NUL.
  739. -//  Simply using a TST instruction checks all four bytes for NULs in one
  740. -//  go.
  741. -    uqsub8  temp,   mask,   word
  742. -    tst     temp,           temp
  743. -.endm
  744. -
  745. -.text
  746. -.align 4
  747. -.long 0x0           // padding
  748. -.long 0x01010101    // mask for use in finding NULs
  749. +#ifdef __ARMEB__
  750. +#define S2LO       lsl
  751. +#define S2HI       lsr
  752. +#else
  753. +#define S2LO       lsr
  754. +#define S2HI       lsl
  755. +#endif
  756. +
  757. +    .text
  758. +    .thumb
  759. +    .syntax unified
  760. +
  761. +/* Parameters and result.  */
  762. +#define srcin      r0
  763. +#define result     r0
  764. +
  765. +/* Internal variables.  */
  766. +#define src        r1
  767. +#define data1a     r2
  768. +#define data1b     r3
  769. +#define const_m1   r12
  770. +#define const_0        r4
  771. +#define tmp1       r4      /* Overlaps const_0  */
  772. +#define tmp2       r5
  773. +
  774.  ENTRY(strlen)
  775. -//  Establish stack frame, load mask that we will use to find NUL bytes,
  776. -//  and set aside a copy of the pointer to the string.
  777. -    push    {r7,lr}
  778. -    mov     r7,     sp
  779. -    ldr     mask,   (strlen-4)
  780. -    add        save,   addr,   #4
  781. -
  782. -//  Load the aligned word that contains the start of the string, then OR
  783. -//  0x01 into any bytes that preceed the start of the string to prevent
  784. -//  false positives when we check for NUL bytes.
  785. -    and     temp,   addr,   #3
  786. -    bic     addr,   addr,   #3
  787. -    lsl     temp,   temp,   #3
  788. -    ldr     word,  [addr],  #4
  789. -    rsb     temp,   temp,   #32
  790. -    orr     word,   word,   mask, lsr temp
  791. -
  792. -//  Check if the string ends in the first word.  If so, don't load any
  793. -//  more of the string; instead jump directly to the cleanup code.
  794. -    IfWordDoesntContainNUL_SetZ
  795. -    bne     1f
  796. -
  797. -.align 4
  798. -//  Load one word of the string on each iteration, and check it for NUL
  799. -//  bytes.  If a NUL is found, fall through into the cleanup code.
  800. -0:  ldr     word,  [addr],  #4
  801. -    IfWordDoesntContainNUL_SetZ
  802. -    beq        0b
  803. -
  804. -//  The last word that we loaded contained a NUL.  Subtracting the saved
  805. -//  pointer from the current pointer gives us the number of bytes from
  806. -//  the start of the string to the word containing the NUL.
  807. -1:  sub     indx,   addr,   save
  808. -//  To that we add the index of the first NUL byte in the word, computed
  809. -//  using REV and CLZ followed by a shift.
  810. -    rev     temp,           temp
  811. -    clz     temp,           temp
  812. -    add     indx,   indx,   temp, lsr #3
  813. -    pop     {r7,pc}
  814. -
  815. -END(strlen)
  816. +    .p2align 6
  817. +    pld     [srcin, #0]
  818. +    strd    r4, r5, [sp, #-8]!
  819. +    bic     src, srcin, #7
  820. +    mvn     const_m1, #0
  821. +    ands    tmp1, srcin, #7        /* (8 - bytes) to alignment.  */
  822. +    pld     [src, #32]
  823. +    bne.w   .L_misaligned8
  824. +    mov     const_0, #0
  825. +    mov     result, #-8
  826. +.L_loop_aligned:
  827. +   /* Bytes 0-7.  */
  828. +    ldrd    data1a, data1b, [src]
  829. +    pld     [src, #64]
  830. +    add     result, result, #8
  831. +.L_start_realigned:
  832. +    uadd8   data1a, data1a, const_m1   /* Saturating GE<0:3> set.  */
  833. +    sel     data1a, const_0, const_m1  /* Select based on GE<0:3>.  */
  834. +    uadd8   data1b, data1b, const_m1
  835. +    sel     data1b, data1a, const_m1   /* Only used if d1a == 0.  */
  836. +    cbnz    data1b, .L_null_found
  837. +
  838. +   /* Bytes 8-15.  */
  839. +    ldrd    data1a, data1b, [src, #8]
  840. +    uadd8   data1a, data1a, const_m1   /* Saturating GE<0:3> set.  */
  841. +    add     result, result, #8
  842. +    sel     data1a, const_0, const_m1  /* Select based on GE<0:3>.  */
  843. +    uadd8   data1b, data1b, const_m1
  844. +    sel     data1b, data1a, const_m1   /* Only used if d1a == 0.  */
  845. +    cbnz    data1b, .L_null_found
  846. +
  847. +   /* Bytes 16-23.  */
  848. +    ldrd    data1a, data1b, [src, #16]
  849. +    uadd8   data1a, data1a, const_m1   /* Saturating GE<0:3> set.  */
  850. +    add     result, result, #8
  851. +    sel     data1a, const_0, const_m1  /* Select based on GE<0:3>.  */
  852. +    uadd8   data1b, data1b, const_m1
  853. +    sel     data1b, data1a, const_m1   /* Only used if d1a == 0.  */
  854. +    cbnz    data1b, .L_null_found
  855. +
  856. +   /* Bytes 24-31.  */
  857. +    ldrd    data1a, data1b, [src, #24]
  858. +    add     src, src, #32
  859. +    uadd8   data1a, data1a, const_m1   /* Saturating GE<0:3> set.  */
  860. +    add     result, result, #8
  861. +    sel     data1a, const_0, const_m1  /* Select based on GE<0:3>.  */
  862. +    uadd8   data1b, data1b, const_m1
  863. +    sel     data1b, data1a, const_m1   /* Only used if d1a == 0.  */
  864. +    cmp     data1b, #0
  865. +    beq     .L_loop_aligned
  866. +
  867. +.L_null_found:
  868. +    cmp     data1a, #0
  869. +    itt     eq
  870. +    addeq   result, result, #4
  871. +    moveq   data1a, data1b
  872. +#ifndef __ARMEB__
  873. +    rev     data1a, data1a
  874. +#endif
  875. +    clz     data1a, data1a
  876. +    ldrd    r4, r5, [sp], #8
  877. +    add     result, result, data1a, lsr #3 /* Bits -> Bytes.  */
  878. +    bx      lr
  879. +
  880. +.L_misaligned8:
  881. +    ldrd    data1a, data1b, [src]
  882. +    and     tmp2, tmp1, #3
  883. +    rsb     result, tmp1, #0
  884. +    lsl     tmp2, tmp2, #3         /* Bytes -> bits.  */
  885. +    tst     tmp1, #4
  886. +    pld     [src, #64]
  887. +    S2HI    tmp2, const_m1, tmp2
  888. +    orn     data1a, data1a, tmp2
  889. +    itt     ne
  890. +    ornne   data1b, data1b, tmp2
  891. +    movne   data1a, const_m1
  892. +    mov     const_0, #0
  893. +    b       .L_start_realigned
  894. +END(strlen)
  895. \ No newline at end of file
  896. diff --git a/linker/Android.mk b/linker/Android.mk
  897. index 3d7aacb2f..a8f82b4bf 100644
  898. --- a/linker/Android.mk
  899. +++ b/linker/Android.mk
  900. @@ -78,10 +78,6 @@ LOCAL_MODULE_STEM_32 := linker
  901.  LOCAL_MODULE_STEM_64 := linker64
  902.  LOCAL_MULTILIB := both
  903.  
  904. -# Leave the symbols in the shared library so that stack unwinders can produce
  905. -# meaningful name resolution.
  906. -LOCAL_STRIP_MODULE := keep_symbols
  907. -
  908.  # Insert an extra objcopy step to add prefix to symbols. This is needed to prevent gdb
  909.  # looking up symbols in the linker by mistake.
  910.  #
  911.  
  912. build/.git
  913. diff --git a/core/Makefile b/core/Makefile
  914. index c089e38a6..d1727c102 100644
  915. --- a/core/Makefile
  916. +++ b/core/Makefile
  917. @@ -2015,9 +2015,9 @@ ifeq ($(build_ota_package),true)
  918.  name := $(TARGET_PRODUCT)
  919.  ifeq ($(TARGET_BUILD_TYPE),debug)
  920.    name := $(name)_debug
  921. -  # Assume non-release recoveries skip signature check
  922. -  extra_ota_args := --no_signing
  923.  endif
  924. +# Assume non-release recoveries skip signature check
  925. +extra_ota_args := --no_signing
  926.  
  927.  INTERNAL_OTA_PACKAGE_TARGET := $(PRODUCT_OUT)/$(name)-$(ROM_VERSION).zip
  928.  
  929. diff --git a/core/combo/TARGET_linux-arm.mk b/core/combo/TARGET_linux-arm.mk
  930. index 510aae52f..858bb4eca 100644
  931. --- a/core/combo/TARGET_linux-arm.mk
  932. +++ b/core/combo/TARGET_linux-arm.mk
  933. @@ -97,7 +97,6 @@ ifeq ($(FORCE_ARM_DEBUGGING),true)
  934.  endif
  935.  
  936.  $(combo_2nd_arch_prefix)TARGET_GLOBAL_CFLAGS += \
  937. -           -msoft-float \
  938.             -ffunction-sections \
  939.             -fdata-sections \
  940.             -funwind-tables \
  941. diff --git a/core/main.mk b/core/main.mk
  942. index c19ab3d99..8efe39d09 100644
  943. --- a/core/main.mk
  944. +++ b/core/main.mk
  945. @@ -371,13 +371,13 @@ endif
  946.  
  947.  ## user/userdebug ##
  948.  
  949. -user_variant := $(filter user userdebug,$(TARGET_BUILD_VARIANT))
  950. +user_variant := userdebug
  951.  enable_target_debugging := true
  952.  tags_to_install :=
  953.  ifneq (,$(user_variant))
  954.    # Target is secure in user builds.
  955.    ADDITIONAL_DEFAULT_PROPERTIES += ro.secure=1
  956. -  ADDITIONAL_DEFAULT_PROPERTIES += security.perf_harden=1
  957. +  ADDITIONAL_DEFAULT_PROPERTIES += security.perf_harden=0
  958.  
  959.    ifeq ($(user_variant),user)
  960.      ADDITIONAL_DEFAULT_PROPERTIES += ro.adb.secure=1
  961.  
  962. build/soong/.git
  963. diff --git a/cc/arm_device.go b/cc/arm_device.go
  964. index 7212c4f..dcb8b90 100644
  965. --- a/cc/arm_device.go
  966. +++ b/cc/arm_device.go
  967. @@ -29,7 +29,6 @@ var (
  968.     armCflags = []string{
  969.         "-fno-exceptions", // from build/core/combo/select.mk
  970.         "-Wno-multichar",  // from build/core/combo/select.mk
  971. -       "-msoft-float",
  972.         "-ffunction-sections",
  973.         "-fdata-sections",
  974.         "-funwind-tables",
  975.  
  976. device/oneplus/oneplus3/.git
  977. diff --git a/BoardConfig.mk b/BoardConfig.mk
  978. index c82a8b65..021b8f28 100644
  979. --- a/BoardConfig.mk
  980. +++ b/BoardConfig.mk
  981. @@ -56,7 +56,7 @@ BOARD_USERDATAIMAGE_PARTITION_SIZE := 57436708864
  982.  BOARD_FLASH_BLOCK_SIZE := 262144
  983.  
  984.  # Kernel
  985. -BOARD_KERNEL_CMDLINE := androidboot.hardware=qcom ehci-hcd.park=3 lpm_levels.sleep_disabled=1 cma=32M@0-0xffffffff
  986. +BOARD_KERNEL_CMDLINE := androidboot.hardware=qcom ehci-hcd.park=3 lpm_levels.sleep_disabled=1 cma=32M@0-0xffffffff androidboot.selinux=permissive
  987.  BOARD_KERNEL_BASE        := 0x80000000
  988.  BOARD_KERNEL_PAGESIZE    := 4096
  989.  BOARD_RAMDISK_OFFSET := 0x01000000
  990.  
  991. external/f2fs-tools/.git
  992. diff --git a/Android.mk b/Android.mk
  993. index 0dca860..b8b4661 100644
  994. --- a/Android.mk
  995. +++ b/Android.mk
  996. @@ -6,12 +6,6 @@ ifneq (,$(filter linux darwin,$(HOST_OS)))
  997.  # The versions depend on $(LOCAL_PATH)/VERSION
  998.  common_CFLAGS := -DF2FS_MAJOR_VERSION=1 -DF2FS_MINOR_VERSION=8 -DF2FS_TOOLS_VERSION=\"1.8.0\" -DF2FS_TOOLS_DATE=\"2017-02-03\"
  999.  
  1000. -# fsck.f2fs forces a full file system scan whenever /proc/version changes
  1001. -# Perform this check only when it's a release build
  1002. -ifneq ($(TARGET_BUILD_VARIANT), user)
  1003. -    common_CFLAGS += -DDISABLE_VERSION_CHECK
  1004. -endif
  1005. -
  1006.  # external/e2fsprogs/lib is needed for uuid/uuid.h
  1007.  common_C_INCLUDES := $(LOCAL_PATH)/include external/e2fsprogs/lib/ $(LOCAL_PATH)/mkfs
  1008.  
  1009.  
  1010. external/zlib/.git
  1011. diff --git a/src/deflate.c b/src/deflate.c
  1012. index 1b0bea7..db54bec 100644
  1013. --- a/src/deflate.c
  1014. +++ b/src/deflate.c
  1015. @@ -282,7 +282,7 @@ int ZEXPORT deflateInit2_(strm, level, method, windowBits, memLevel, strategy,
  1016.  #ifdef FASTEST
  1017.      if (level != 0) level = 1;
  1018.  #else
  1019. -    if (level == Z_DEFAULT_COMPRESSION) level = 6;
  1020. +    if (level == Z_DEFAULT_COMPRESSION) level = 3;
  1021.  #endif
  1022.  
  1023.      if (windowBits < 0) { /* suppress zlib wrapper */
  1024. @@ -579,7 +579,7 @@ int ZEXPORT deflateParams(strm, level, strategy)
  1025.  #ifdef FASTEST
  1026.      if (level != 0) level = 1;
  1027.  #else
  1028. -    if (level == Z_DEFAULT_COMPRESSION) level = 6;
  1029. +    if (level == Z_DEFAULT_COMPRESSION) level = 3;
  1030.  #endif
  1031.      if (level < 0 || level > 9 || strategy < 0 || strategy > Z_FIXED) {
  1032.          return Z_STREAM_ERROR;
  1033.  
  1034. system/core/.git
  1035. diff --git a/adb/Android.mk b/adb/Android.mk
  1036. index 8f56d744e..d0dc19fd5 100644
  1037. --- a/adb/Android.mk
  1038. +++ b/adb/Android.mk
  1039. @@ -327,12 +327,9 @@ LOCAL_CFLAGS := \
  1040.      -D_GNU_SOURCE \
  1041.      -Wno-deprecated-declarations \
  1042.  
  1043. -LOCAL_CFLAGS += -DALLOW_ADBD_NO_AUTH=$(if $(filter userdebug eng,$(TARGET_BUILD_VARIANT)),1,0)
  1044. -
  1045. -ifneq (,$(filter userdebug eng,$(TARGET_BUILD_VARIANT)))
  1046. +LOCAL_CFLAGS += -DALLOW_ADBD_NO_AUTH=1
  1047.  LOCAL_CFLAGS += -DALLOW_ADBD_DISABLE_VERITY=1
  1048.  LOCAL_CFLAGS += -DALLOW_ADBD_ROOT=1
  1049. -endif
  1050.  
  1051.  LOCAL_MODULE := adbd
  1052.  
  1053. diff --git a/adb/daemon/main.cpp b/adb/daemon/main.cpp
  1054. index 4721e2fbb..c857020e7 100644
  1055. --- a/adb/daemon/main.cpp
  1056. +++ b/adb/daemon/main.cpp
  1057. @@ -44,66 +44,11 @@
  1058.  static const char* root_seclabel = nullptr;
  1059.  
  1060.  static void drop_capabilities_bounding_set_if_needed() {
  1061. -#ifdef ALLOW_ADBD_ROOT
  1062. -    char value[PROPERTY_VALUE_MAX];
  1063. -    property_get("ro.debuggable", value, "");
  1064. -    if (strcmp(value, "1") == 0) {
  1065. -        return;
  1066. -    }
  1067. -#endif
  1068. -    for (int i = 0; prctl(PR_CAPBSET_READ, i, 0, 0, 0) >= 0; i++) {
  1069. -        if (i == CAP_SETUID || i == CAP_SETGID) {
  1070. -            // CAP_SETUID CAP_SETGID needed by /system/bin/run-as
  1071. -            continue;
  1072. -        }
  1073. -
  1074. -        if (prctl(PR_CAPBSET_DROP, i, 0, 0, 0) == -1) {
  1075. -            PLOG(FATAL) << "Could not drop capabilities";
  1076. -        }
  1077. -    }
  1078. +    return;
  1079.  }
  1080.  
  1081.  static bool should_drop_privileges() {
  1082. -#if defined(ALLOW_ADBD_ROOT)
  1083. -    char value[PROPERTY_VALUE_MAX];
  1084. -
  1085. -    // The properties that affect `adb root` and `adb unroot` are ro.secure and
  1086. -    // ro.debuggable. In this context the names don't make the expected behavior
  1087. -    // particularly obvious.
  1088. -    //
  1089. -    // ro.debuggable:
  1090. -    //   Allowed to become root, but not necessarily the default. Set to 1 on
  1091. -    //   eng and userdebug builds.
  1092. -    //
  1093. -    // ro.secure:
  1094. -    //   Drop privileges by default. Set to 1 on userdebug and user builds.
  1095. -    property_get("ro.secure", value, "1");
  1096. -    bool ro_secure = (strcmp(value, "1") == 0);
  1097. -
  1098. -    property_get("ro.debuggable", value, "");
  1099. -    bool ro_debuggable = (strcmp(value, "1") == 0);
  1100. -
  1101. -    // Drop privileges if ro.secure is set...
  1102. -    bool drop = ro_secure;
  1103. -
  1104. -    property_get("service.adb.root", value, "");
  1105. -    bool adb_root = (strcmp(value, "1") == 0);
  1106. -    bool adb_unroot = (strcmp(value, "0") == 0);
  1107. -
  1108. -    // ... except "adb root" lets you keep privileges in a debuggable build.
  1109. -    if (ro_debuggable && adb_root) {
  1110. -        drop = false;
  1111. -    }
  1112. -
  1113. -    // ... and "adb unroot" lets you explicitly drop privileges.
  1114. -    if (adb_unroot) {
  1115. -        drop = true;
  1116. -    }
  1117. -
  1118. -    return drop;
  1119. -#else
  1120. -    return true; // "adb root" not allowed, always drop privileges.
  1121. -#endif // ALLOW_ADBD_ROOT
  1122. +    return false;
  1123.  }
  1124.  
  1125.  static void drop_privileges(int server_port) {
  1126. @@ -143,11 +88,6 @@ static void drop_privileges(int server_port) {
  1127.          // minijail_enter() will abort if any priv-dropping step fails.
  1128.          minijail_enter(jail.get());
  1129.  
  1130. -        if (root_seclabel != nullptr) {
  1131. -            if (selinux_android_setcon(root_seclabel) < 0) {
  1132. -                LOG(FATAL) << "Could not set SELinux context";
  1133. -            }
  1134. -        }
  1135.          std::string error;
  1136.          std::string local_name =
  1137.              android::base::StringPrintf("tcp:%d", server_port);
  1138. @@ -170,9 +110,7 @@ int adbd_main(int server_port) {
  1139.      // descriptor will always be open.
  1140.      adbd_cloexec_auth_socket();
  1141.  
  1142. -    if (ALLOW_ADBD_NO_AUTH && property_get_bool("ro.adb.secure", 0) == 0) {
  1143. -        auth_required = false;
  1144. -    }
  1145. +    auth_required = false;
  1146.  
  1147.      adbd_auth_init();
  1148.  
  1149. diff --git a/init/Android.mk b/init/Android.mk
  1150. index e00589ca8..e099b6ecf 100644
  1151. --- a/init/Android.mk
  1152. +++ b/init/Android.mk
  1153. @@ -4,12 +4,7 @@ LOCAL_PATH:= $(call my-dir)
  1154.  
  1155.  # --
  1156.  
  1157. -ifneq (,$(filter userdebug eng,$(TARGET_BUILD_VARIANT)))
  1158.  init_options += -DALLOW_LOCAL_PROP_OVERRIDE=1 -DALLOW_PERMISSIVE_SELINUX=1
  1159. -else
  1160. -init_options += -DALLOW_LOCAL_PROP_OVERRIDE=0 -DALLOW_PERMISSIVE_SELINUX=0
  1161. -endif
  1162. -
  1163.  init_options += -DLOG_UEVENTS=0
  1164.  
  1165.  ifneq ($(TARGET_INIT_COLDBOOT_TIMEOUT),)
  1166.  
  1167. vendor/pa/.git
  1168. diff --git a/products/oneplus3/pa.dependencies b/products/oneplus3/pa.dependencies
  1169. index 5991fe8..fb7f5d3 100644
  1170. --- a/products/oneplus3/pa.dependencies
  1171. +++ b/products/oneplus3/pa.dependencies
  1172. @@ -1,20 +1,38 @@
  1173.  [
  1174.      {
  1175. +        "remote":       "github-ssh",
  1176. +        "repository":   "TheCrazyLex/op3-device",
  1177. +        "target_path":  "device/oneplus/oneplus3",
  1178. +        "revision":     "nougat-mr1"
  1179. +    },
  1180. +    {
  1181. +        "remote":       "github-ssh",
  1182. +        "repository":   "TheCrazyLex/kernel_oneplus_msm8996",
  1183. +        "target_path":  "kernel/oneplus/msm8996",
  1184. +        "revision":     "nougat-mr1"
  1185. +    },
  1186. +    {
  1187. +        "remote":       "github-ssh",
  1188. +        "repository":   "TheCrazyLex/vendor_oneplus-b",
  1189. +        "target_path":  "vendor/oneplus",
  1190. +        "revision":     "nougat-mr2"
  1191. +    },
  1192. +    {
  1193.          "remote":       "github",
  1194.          "repository":   "AOSPA/android_hardware_qcom_audio",
  1195.          "target_path":  "hardware/qcom/audio",
  1196. -        "revision":     "nougat-mr1-8996"
  1197. +        "revision":     "nougat-mr2-8996"
  1198.      },
  1199.      {
  1200.          "remote":       "github",
  1201.          "repository":   "AOSPA/android_hardware_qcom_display",
  1202.          "target_path":  "hardware/qcom/display",
  1203. -        "revision":     "nougat-mr1-8996"
  1204. +        "revision":     "nougat-mr2-8996"
  1205.      },
  1206.      {
  1207.          "remote":       "github",
  1208.          "repository":   "AOSPA/android_hardware_qcom_media",
  1209.          "target_path":  "hardware/qcom/media",
  1210. -        "revision":     "nougat-mr1-8996"
  1211. +        "revision":     "nougat-mr2-8996"
  1212.      }
  1213.  ]
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