shift_reg

`timescale 1ns / 1ps

module shift_reg(
    input clk,
    input reset,
    input enable,
    input mux_load,
    input[31:0] inp,
    output reg s_out
);

reg[31:0] shifted_reg;
wire[31:0] shifted_next_value;
assign shifted_next_value = (mux_load) ? inp : shifted_reg >> 1;
always @(posedge reset) begin
    if (reset) begin
            shifted_reg <= 0;
            s_out <= shifted_reg[0];
    end
end

always @(posedge clk) begin
    if (mux_load) begin
            shifted_reg <= inp;
    end else begin
            shifted_reg <= shifted_next_value;
    end
    if (enable) begin
            s_out <= shifted_reg[0];
    end
end
endmodule