Main_ALU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity main_alu is
    port (
        Left_Operand_Reg1     : in  std_logic_vector(31 downto 0); -- AKA register 1 output
        Right_Operand_Reg2_Imm_Shamt  : in std_logic_vector(31 downto 0); -- AKA register 2/imm/shamt output
        ALU_Control : in std_logic_vector(3 downto 0);

        Result  : out std_logic_vector(31 downto 0);
        Z_Flag : out std_logic
    );
end entity main_alu;

architecture dataflow of main_alu is
    -- Constants
    constant ALU_AND : std_logic_vector(3 downto 0) := "0000";
    constant ALU_OR : std_logic_vector(3 downto 0) := "0001";
    constant ALU_ADD : std_logic_vector(3 downto 0) := "0010";
    --constant ALU_XOR : std_logic_vector(3 downto 0) := "0011";
    constant ALU_SUB : std_logic_vector(3 downto 0) := "0110";
    constant ALU_PASS_Reg2_Imm_FLAGS : std_logic_vector(3 downto 0) := "0111";
    constant ALU_PASS_Reg1_FLAGS : std_logic_vector(3 downto 0) := "1000";
    --constant ALU_ADD_UNSIGNED : std_logic_vector(3 downto 0) := "1010";
    --constant ALU_NOR : std_logic_vector(3 downto 0) := "1100";
    constant ALU_SHIFT_LEFT : std_logic_vector(3 downto 0) := "1101";
    --constant ALU_SUB_UNSIGNED : std_logic_vector(3 downto 0) := "1110";
    constant ALU_SHIFT_RIGHT : std_logic_vector(3 downto 0) := "1111";

    -- Signals
    signal Internal_Result : std_logic_vector(31 downto 0);
    signal Internal_Z_Flag : std_logic;
begin
    -- Add result together
    with ALU_Control select
        Internal_Result <= Left_Operand_Reg1 and Right_Operand_Reg2_Imm_Shamt when ALU_AND, -- AND

                           Left_Operand_Reg1 or Right_Operand_Reg2_Imm_Shamt when ALU_OR, -- OR

                           std_logic_vector(signed(Left_Operand_Reg1) + signed(Right_Operand_Reg2_Imm_Shamt)) when ALU_ADD, -- add

                           --Left_Operand_Reg1 xor Right_Operand_Reg2_Imm_Shamt when ALU_XOR, -- XOR, not used

                           std_logic_vector(signed(Left_Operand_Reg1) - signed(Right_Operand_Reg2_Imm_Shamt)) when ALU_SUB, -- subtract

                           Left_Operand_Reg1 when ALU_PASS_Reg2_Imm_FLAGS, -- Pass Register 2/imm, Set Z Flag

                           Right_Operand_Reg2_Imm_Shamt when ALU_PASS_Reg1_FLAGS, -- Pass Register 1

                           --std_logic_vector(unsigned(Left_Operand_Reg1) + unsigned(Right_Operand_Reg2_Imm_Shamt)) when ALU_ADD_UNSIGNED, -- add unsigned, not used

                           --not(Left_Operand_Reg1 or Right_Operand_Reg2_Imm_Shamt) when ALU_NOR, -- NOR, not used

                           std_logic_vector(shift_left(signed(Left_Operand_Reg1), to_integer(unsigned(Right_Operand_Reg2_Imm_Shamt)))) when ALU_SHIFT_LEFT, -- Shift Left Logical

                           --std_logic_vector(unsigned(Left_Operand_Reg1) - unsigned(Right_Operand_Reg2_Imm_Shamt)) when ALU_SUB_UNSIGNED, -- subtract unsigned, not used

                           std_logic_vector(shift_right(signed(Left_Operand_Reg1), to_integer(unsigned(Right_Operand_Reg2_Imm_Shamt)))) when ALU_SHIFT_RIGHT, -- Shift Right Logical

                           (others => 'X') when others;

        -- Set Flags
        Internal_Z_Flag <= '1' when (ALU_Control = ALU_PASS_Reg2_Imm_FLAGS or ALU_Control = ALU_PASS_Reg1_FLAGS) and to_integer(signed(Internal_Result)) = 0 else
                  '0' when (ALU_Control = ALU_PASS_Reg2_Imm_FLAGS or ALU_Control = ALU_PASS_Reg1_FLAGS) and to_integer(signed(Internal_Result)) /= 0
                  else Internal_Z_Flag;

       -- Final ALU_ADD
       Result <= Internal_Result;
       Z_Flag <= Internal_Z_Flag;

end architecture dataflow;