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- ***** Spice Netlist for Cell 'readsrx' *****
- ************** Module readsrx **************
- xi0 b bb wl n2 n0 srx
- v0 n2 gnd dc='0' ac='0'
- vdd n0 n2 dc='5' ac='0'
- vp n1 n2 dc='5' ac='0'
- vwl wl n2 pulse 0 5v 12ns 200ps 200ps 10ns 30ns
- vread read n2 pulse 0v 5v 10ns 200ps 200ps 15ns 30ns
- c0 gnd b 1280f
- m2 b gnd gnd gnd
- + NMOS4 l='0.4u' w='0.8u' m='127'
- c1 gnd bb 1280f
- m3 bb gnd gnd gnd
- + NMOS4 l='0.4u' w='0.8u' m='127'
- m4 gnd wl gnd gnd
- + NMOS4 l='0.4u' w='0.8u' m='254'
- c2 gnd wl 2560f
- m8 n1 wl n1 gnd
- + NMOS4 l='0.4u' w='0.8u' m='254'
- m1 b read n1 n1
- + PMOS4 l='0.4u' w='2.0u' m='1'
- m7 bb read b n1
- + PMOS4 l='0.4u' w='2.0u' m='1'
- m0 bb read n1 n1
- + PMOS4 l='0.4u' w='2.0u' m='1'
- m6 b write gnd gnd
- + NMOS4 l='0.4u' w='1.5u' m='1'
- m5 bb n3 gnd gnd
- + NMOS4 l='0.4u' w='1.5u' m='1'
- xi1 gnd n4 en b bb dout samp
- vpp n4 gnd dc='5' ac='0'
- v2 en gnd pulse 0 5v 23ns 200ps 200ps 10ns 60ns
- xi2 data wen write n3 n5 gnd wd
- vwd n5 gnd dc='5' ac='0'
- v1 wen gnd pulse 0 5v 41ns 200ps 200ps 17ns 60ns
- v3 data gnd pulse 0 5v 0ns 200ps 200ps 80ns 160ns
- ************** Module samp **************
- .subckt samp gnd vdd en bit bitb dout example_param=1.0
- m0 n0 en gnd gnd
- + NMOS4 l='0.4u' w='1.8u' m='1'
- m1 n0 n1 dout gnd
- + NMOS4 l='0.4u' w='1.8u' m='1'
- m2 n1 dout n0 gnd
- + NMOS4 l='0.4u' w='1.8u' m='1'
- m3 vdd n1 dout vdd
- + PMOS4 l='0.4u' w='3.6u' m='1'
- m4 n1 dout vdd vdd
- + PMOS4 l='0.4u' w='3.6u' m='1'
- m5 bit en dout vdd
- + PMOS4 l='0.4u' w='4.8u' m='1'
- m6 n1 en bitb vdd
- + PMOS4 l='0.4u' w='4.8u' m='1'
- .ends samp
- ************** Module srx **************
- .subckt srx bit bitb ws agnd avdd example_param=1.0
- m3 bit ws n0 agnd
- + NMOS4 l='0.4u' w='0.8u' m='1'
- m4 n1 ws bitb agnd
- + NMOS4 l='0.4u' w='0.8u' m='1'
- m1 agnd n1 n0 agnd
- + NMOS4 l='0.4u' w='1.6u' m='1'
- m2 n1 n0 agnd agnd
- + NMOS4 l='0.4u' w='1.6u' m='1'
- m6 n1 n0 avdd avdd
- + PMOS4 l='0.8u' w='0.6u' m='1'
- m5 avdd n1 n0 avdd
- + PMOS4 l='0.8u' w='0.6u' m='1'
- .ends srx
- ************** Module wd **************
- .subckt wd din wen bit bitb vdd gnd example_param=1.0
- m1 n2 din vdd vdd
- + PMOS4 l='0.4u' w='1.4u' m='1'
- m2 n2 din gnd gnd
- + NMOS4 l='0.4u' w='0.8u' m='1'
- m5 n0 din n4 gnd
- + NMOS4 l='0.4u' w='1.4u' m='1'
- m6 n4 wen gnd gnd
- + NMOS4 l='0.4u' w='1.4u' m='1'
- m3 n0 din vdd vdd
- + PMOS4 l='0.4u' w='1.4u' m='1'
- m4 n0 wen vdd vdd
- + PMOS4 l='0.4u' w='1.4u' m='1'
- m7 n1 n2 vdd vdd
- + PMOS4 l='0.4u' w='1.4u' m='1'
- m8 n1 wen vdd vdd
- + PMOS4 l='0.4u' w='1.4u' m='1'
- m9 n1 n2 n3 gnd
- + NMOS4 l='0.4u' w='1.4u' m='1'
- m10 n3 wen gnd gnd
- + NMOS4 l='0.4u' w='1.4u' m='1'
- m11 bit n0 gnd gnd
- + NMOS4 l='0.4u' w='0.8u' m='1'
- m12 bitb n1 vdd vdd
- + PMOS4 l='0.4u' w='1.4u' m='1'
- m13 bitb n1 gnd gnd
- + NMOS4 l='0.4u' w='0.8u' m='1'
- m14 bit n0 vdd vdd
- + PMOS4 l='0.4u' w='1.4u' m='1'
- .ends wd
- **************Model File***************
- .MODEL NMOS4 NMOS ( LEVEL = 49
- +VERSION = 3.1 TNOM = 27 TOX = 7.6E-9
- +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.4964448
- +K1 = 0.5307769 K2 = 0.0199705 K3 = 0.2963637
- +K3B = 0.2012165 W0 = 2.836319E-6 NLX = 2.894802E-7
- +DVT0W = 0 DVT1W = 5.3E6 DVT2W = -0.032
- +DVT0 = 0.112017 DVT1 = 0.2453972 DVT2 = -0.171915
- +U0 = 444.9381976 UA = 2.921284E-10 UB = 1.773281E-18
- +UC = 7.067896E-11 VSAT = 1.130785E5 A0 = 1.1356246
- +AGS = 0.2810374 B0 = 2.844393E-7 B1 = 5E-6
- +KETA = -7.8181E-3 A1 = 0 A2 = 1
- +RDSW = 925.2701982 PRWG = -1E-3 PRWB = -1E-3
- +WR = 1 WINT = 7.186965E-8 LINT = 1.735515E-9
- +XL = -2E-8 XW = 0 DWG = -1.712973E-8
- +DWB = 5.851691E-9 VOFF = -0.132935 NFACTOR = 0.5710974
- +CIT = 0 CDSC = 8.607229E-4 CDSCD = 0
- +CDSCB = 0 ETA0 = 2.128321E-3 ETAB = 0
- +DSUB = 0.0257957 PCLM = 0.6766314 PDIBLC1 = 1
- +PDIBLC2 = 1.787424E-3 PDIBLCB = 0 DROUT = 0.7873539
- +PSCBE1 = 6.973485E9 PSCBE2 = 1.46235E-7 PVAG = 0.05
- +DELTA = 0.01 MOBMOD = 1 PRT = 0
- +UTE = -1.5 KT1 = -0.11 KT1L = 0
- +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
- +UC1 = -5.6E-11 AT = 3.3E4 WL = 0
- +WLN = 1 WW = 0 WWN = 1
- +WWL = 0 LL = 0 LLN = 1
- +LW = 0 LWN = 1 LWL = 0
- +CAPMOD = 2 CGDO = 1.96E-10 CGSO = 1.96E-10
- +CGBO = 0 CJ = 9.276962E-4 PB = 0.8157962
- +MJ = 0.3557696 CJSW = 3.181055E-10 PBSW = 0.6869149
- +MJSW = 0.1 PVTH0 = -0.0252481 PRDSW = -96.4502805
- +PK2 = -4.805372E-3 WKETA = -7.643187E-4 LKETA = -0.0129496 )
- .MODEL PMOS4 PMOS ( LEVEL = 49
- +VERSION = 3.1 TNOM = 27 TOX = 7.6E-9
- +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.6636594
- +K1 = 0.4564781 K2 = -0.019447 K3 = 39.382919
- +K3B = -2.8930965 W0 = 2.655585E-6 NLX = 1.51028E-7
- +DVT0W = 0 DVT1W = 5.3E6 DVT2W = -0.032
- +DVT0 = 1.1744581 DVT1 = 0.7631128 DVT2 = -0.1035171
- +U0 = 151.3305606 UA = 2.061211E-10 UB = 1.823477E-18
- +UC = -8.97321E-12 VSAT = 9.915604E4 A0 = 1.1210053
- +AGS = 0.3961954 B0 = 6.493139E-7 B1 = 4.273215E-6
- +KETA = -9.27E-3 A1 = 0 A2 = 1
- +RDSW = 2.30725E3 PRWG = -1E-3 PRWB = 0
- +WR = 1 WINT = 5.962233E-8 LINT = 4.30928E-9
- +XL = -2E-8 XW = 0 DWG = -1.596201E-8
- +DWB = 1.378919E-8 VOFF = -0.15 NFACTOR = 2
- +CIT = 0 CDSC = 6.593084E-4 CDSCD = 0
- +CDSCB = 0 ETA0 = 0.0286461 ETAB = 0
- +DSUB = 0.2436027 PCLM = 4.3597508 PDIBLC1 = 7.447024E-4
- +PDIBLC2 = 4.256073E-3 PDIBLCB = 0 DROUT = 0.0120292
- +PSCBE1 = 1.347622E10 PSCBE2 = 5E-9 PVAG = 3.669793
- +DELTA = 0.01 MOBMOD = 1 PRT = 0
- +UTE = -1.5 KT1 = -0.11 KT1L = 0
- +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
- +UC1 = -5.6E-11 AT = 3.3E4 WL = 0
- +WLN = 1 WW = 0 WWN = 1
- +WWL = 0 LL = 0 LLN = 1
- +LW = 0 LWN = 1 LWL = 0
- +CAPMOD = 2 CGDO = 2.307E-10 CGSO = 2.307E-10
- +CGBO = 0 CJ = 1.420282E-3 PB = 0.99
- +MJ = 0.5490877 CJSW = 4.773605E-10 PBSW = 0.99
- +MJSW = 0.1997417 PVTH0 = 6.58707E-3 PRDSW = -93.5582228
- +PK2 = 1.011593E-3 WKETA = -0.0101398 LKETA = 6.027967E-3 )
- .param hdout=6.600e-007
- .param hdin=7.400e-007
- .include '../../../SpiceModels/cmos_013_bsim4.mod'
- .include '../../../SpiceModels/bipolar.mod'
- .temp 27
- .param vsupply=5
- .global vdd gnd
- .nodeset V(xi0.n0)=5
- .options post=1 delmax=5p relv=1e-6 reli=1e-6 relmos=1e-6 method=gear
- .tran 1n 160n
- .op
- .save v(b) v(bb) V(xi0.n0) V(xi0.n1) v(read) v(write) v(wl) v(en) v(wen) v(data) v(dout)
- .end
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