module control_unit_sol(

always @(*) begin
    next_state = state + 1;
    t1_oe = 0;
    t1_we = 0;
    t2_oe = 0;
    t2_we = 0;
    regs_oe = 0;
    regs_we = 0;
    regs_addr = 0;
    alu_carry = 0;
    alu_opcode = 0;
    ram_we = 0;
    ram_oe = 0;
    ma_oe = 0;
    ma_we = 0;
    pc_oe = 0;
    pc_we = 0;
    flags_we = 0;
    case(state)
    INIT: next_state = LOAD;
    LOAD_DONE: begin
        verify_t2 = opc[0:6] == 7'b0000000 || opc[1] == 1'b1;
        next_state = EXEC;
    end
    EXEC_DONE: begin
        if ((opc[0:3] == 4'b0100)||(opc[0:3] == 4'b0000 && opc[4:6])) next_state = STORE_DONE;
        else next_state = STORE;
    end
    STORE_DONE: next_state = STORE_DONE;
    // TODO define LOAD, EXEC, STORE here
    LOAD: begin
        t1_we = 1;
        regs_addr = rm[2] ? XB : XA;
        regs_oe = 1;
    end
    LOAD + 1: begin
        t2_we = 1;
        regs_addr = rm[1] ? BB : BA;
        regs_oe = 1;
    end
    LOAD + 2: begin
        alu_opcode = ADC;
        alu_oe = 1;
        t1_oe = 1;
        t2_oe = 1;
        t1_we = 1;

    end
    LOAD + 3: begin
        pc_oe = 1;
        t2_we = 1;
    end
    LOAD + 4: begin
        alu_opcode = ADC;
        alu_oe = 1;
        t2_oe = 1;
        pc_we = 1;
        alu_carry = 1;
        ma_we = 1;
    end
    LOAD + 5: begin
        ma_oe = 1;
    end
    LOAD + 6: begin
        ram_oe = 1;
        t2_we = 1;
    end
    LOAD + 7: begin
        alu_opcode = ADC;
        alu_oe = 1;
        t1_oe = 1;
        t2_oe = 1;
        ma_we = 1;
    end
    LOAD + 8: begin
        ma_oe = 1;
    end
    LOAD + 9: begin
        ram_oe = 1;
        if (d) t2_we = 1;
        else t1_we = 1;
        if (opc[1] == 0 && opc[0:6] != 7'b0000000) next_state = LOAD_DONE;
    end
    LOAD + 10: begin
        regs_oe = 1;
        regs_addr = rg;
        if (d == 0) t2_we = 1;
        else t1_we = 1;
        next_state = LOAD_DONE;
    end
    EXEC: begin

        if (opc[1]) begin
            alu_oe = opc[3];
            casex (opc[4:6])
                3'b00x: alu_opcode = ADC;
                3'b01x: alu_opcode = SBB1;
                3'b100: alu_opcode = AND;
                3'b101: alu_opcode = OR;
                3'b110: alu_opcode = XOR;
                default: alu_opcode = 1'bx;
            endcase
            flags_we = 1;
            t1_oe = 1;
            t2_oe = 1;
            alu_carry = (opc[4:6] == 3'b001 || opc[4:6] == 3'b011) ?
                    flags[FLAG_C] : 0;
            t1_we = opc[3];
            next_state = EXEC_DONE;
        end else begin

            if(opc[3]) begin
                casex (opc[4:6])
                    3'b000: alu_opcode = ADC;
                    3'b001: alu_opcode = SBB1;
                    3'b010: alu_opcode = SBB2;
                    3'b011: alu_opcode = NOT;
                    3'b100: alu_opcode = SHL;
                    3'b101: alu_opcode = SHR;
                    3'b110: alu_opcode = SAR;
                    default: alu_opcode = 1'bx;
                endcase
                alu_carry = opc[4:6] == 3'b000 || opc[4:6] == 3'b001;
                flags_we = 1;
                alu_oe = 1;
                t1_oe = 1;
                t1_we = 1;
                next_state = EXEC_DONE;

            end else begin
                case (opc[4:6])
                    3'b000: begin
                        t1_we = 1;
                        t2_oe = 1;
                        alu_opcode = ADC;
                        alu_oe = 1;
                        next_state = EXEC_DONE;
                    end
                    3'b010, 3'b100: begin
                        regs_addr = SP;
                        regs_oe = 1;
                        t2_we = 1;
                        next_state = PUSH;
                    end
                    3'b101: begin
                        pc_we = 1;
                        t1_oe = 1;
                        alu_opcode = OR;
                        alu_oe = 1;
                        next_state = EXEC_DONE;
                    end
                endcase
            end
        end

    end
    PUSH: begin
        t2_oe = 1;
        alu_opcode = SBB2;
        alu_carry = 1;
        alu_oe = 1;
        regs_we = 1;
        regs_addr = SP;
        ma_we = 1;
    end
    PUSH + 1: begin
        if (opc[4:6] == 3'b100) begin
            pc_oe = 1;
            t2_we = 1;
            next_state = CALL;
        end
        else begin
            ram_we = 1;
            ma_oe = 1;
            t1_oe = 1;
            alu_opcode = OR;
            alu_oe = 1;
            next_state = EXEC_DONE;
        end
    end

    CALL: begin
        ram_we = 1;
        ma_oe = 1;
        alu_opcode = ADC;
        alu_carry = 1;
        alu_oe = 1;
        t2_oe = 1;
    end
    CALL + 1: begin
        t1_oe = 1;
        alu_opcode = OR;
        alu_oe = 1;
        pc_we = 1;
        next_state = EXEC_DONE;
    end

    STORE: begin
        next_state = STORE_DONE;
        alu_opcode = OR;
        alu_oe = 1;
        t1_oe = 1;
        if (d) begin
            regs_addr = rg;
            regs_we = 1;
        end else begin
            ma_oe = 1;
            ram_we = 1;
        end
    end
    default: next_state = INIT;
    endcase
end

endmodule