zbytok

//////// johnson counter testbench //////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Tb_Johnson_counter IS
END Tb_Johnson_counter;

ARCHITECTURE behavior OF Tb_Johnson_counter IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Johnson_counter
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         Q : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

    --Outputs
   signal Q : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Johnson_counter PORT MAP (
          clk => clk,
          rst => rst,
          Q => Q
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;

        rst <= '1';

      wait for 100 ns;

        rst <= '0';

      wait;
   end process;

END;
///////////////////////////////////////////


////////roboti test bench ////////////////

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity robot_mealy_tb is
--  Port ( );
end robot_mealy_tb;

architecture Behavioral of robot_mealy_tb is

    -- Component Declaration for the Unit Under Test (UUT)
    component robot_mealy is
        Port ( clk : in STD_LOGIC;
               rst : in STD_LOGIC;
               din : in STD_LOGIC;
               dout : out STD_LOGIC);
    end component robot_mealy;

    --Output
   signal dout : std_logic;

   --Inputs
   signal rst : std_logic := '0';
   signal clk : std_logic := '0';
   signal din : std_logic := '0';

   -- Clock period definition
   constant clk_period : time := 50 ns;
   constant tester : std_logic_vector(0 to 15) := "0010100000100101";

begin

    -- Instantiate the Unit Under Test (UUT)
    UUT: robot_mealy port map (
        clk => clk,
        rst => rst,
        din => din,
        dout => dout
    );

    -- Clock process definition
    clk_process : process (clk)
    begin
        clk <= not clk after clk_period/2;
    end process;

    -- Stimulus process
    stim_proc: process
    begin
        -- Hold reset state for 100 ns.
        rst <= '1', '0' after 100 ns;

        wait until rst'event and rst = '0';

        for i in 0 to 15 loop
            wait until clk'event and clk = '1';
            din <= tester(i);
        end loop;

        wait;
    end process;

end Behavioral;
/////////////////////////////////////////

/////single port ram//////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity single_port_RAM is
    generic (depth : positive := 2; width : positive := 3);
    Port ( clk : in STD_LOGIC;
           we : in STD_LOGIC;
           Addr : in STD_LOGIC_VECTOR(depth-1 downto 0);
           Din : in STD_LOGIC_VECTOR (width-1 downto 0);
           Dout : out STD_LOGIC_VECTOR (width-1 downto 0));
end single_port_RAM;

/*
architecture Behavioral_package of single_port_RAM is

    package mem is new work.memories generic map (depth => depth, width => width);

begin

    process(clk) is
        variable RAM : mem.RAM_type;

        attribute ram_style : string;
        attribute ram_style of RAM : variable is "block";
    begin
        if rising_edge(clk) then
            if we = '1' then
                mem.write_RAM(RAM, Addr, Din);
            else
                mem.read_RAM(RAM, Addr, Dout);
            end if;
        end if;
    end process;

end Behavioral_package;
*/

architecture Behavioral of single_port_RAM is

    type RAM_type is array (2**depth-1 downto 0) of std_logic_vector (width-1 downto 0);
    signal RAM : RAM_type;


begin

    process(clk) is
    begin
        if rising_edge(clk) then
            if we = '1' then
                RAM(to_integer(unsigned(Addr))) <= Din;
            end if;
        end if;
    end process;

    Dout <= RAM(to_integer(unsigned(Addr)));

end Behavioral;
////////////////////////////

/////////////dual port ram////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


use IEEE.NUMERIC_STD.ALL;


entity dual_port_RAM is
    generic (depth : positive := 2; width : positive := 3);
    Port ( clk : in STD_LOGIC;
           we : in STD_LOGIC;
           rAddr : in STD_LOGIC_VECTOR(depth-1 downto 0);
           wAddr : in STD_LOGIC_VECTOR(depth-1 downto 0);
           Din : in STD_LOGIC_VECTOR (width-1 downto 0);
           Dout : out STD_LOGIC_VECTOR (width-1 downto 0));
end dual_port_RAM;

architecture Behavioral of dual_port_RAM is

    type RAM_type is array (2**depth-1 downto 0) of std_logic_vector (width-1 downto 0);
    signal RAM : RAM_type;

begin

    process(clk) is
    begin
        if rising_edge(clk) then
            if we = '1' then
                RAM(to_integer(unsigned(wAddr))) <= Din;
            end if;
        end if;
    end process;

    Dout <= RAM(to_integer(unsigned(rAddr)));

end Behavioral;
//////////////////////
////////////debouncer///////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity debouncer is
    generic (sys_freq       : natural := 100_000_000; -- in Hz
             stable_time    : natural := 10);  -- in ms
    Port ( clk      : in STD_LOGIC;
           btn      : in STD_LOGIC;
           q        : out STD_LOGIC);
end debouncer;

architecture Structural of debouncer is

    -- Flip-flop D type
    component dff is
        Port ( clk  : in  STD_LOGIC;
               d    : in  STD_LOGIC;
               q    : out  STD_LOGIC);
    end component dff;

    -- Flip-flop D type with enable input
    component dff_en is
        Port ( clk  : in  STD_LOGIC;
               rst  : in  STD_LOGIC;
               d    : in  STD_LOGIC;
               en   : in  STD_LOGIC;
               q    : out  STD_LOGIC);
    end component dff_en;

    component counter is
        generic (up_counter : boolean := TRUE;
                 width      : positive := 8;
                 init_value : natural := 0);
        Port ( clk  : in STD_LOGIC;
               rst  : in STD_LOGIC;
               en   : in STD_LOGIC;
               Y    : out STD_LOGIC_VECTOR (width-1 downto 0);
               o    : out STD_LOGIC);
    end component counter;

    signal q_ff1, q_ff2 : std_logic;
    signal en : std_logic;
    signal counter_rst : std_logic;
    signal detect_zero : std_logic;

begin

    FF1 : dff port map (clk => clk, d => btn, q => q_ff1);
    FF2 : dff port map (clk => clk, d => q_ff1, q => q_ff2);

    counter_rst <= q_ff1 xor q_ff2;

    en <= not detect_zero;
    CNT : counter generic map (up_counter => false, init_value => ((sys_freq*stable_time)/1000), width => 8) port map (clk => clk, rst => counter_rst, en => en, o => detect_zero);

    FF3 : dff_en port map (clk => clk, rst => counter_rst, d => q_ff2, en => detect_zero, q => q);

end Structural;
/////////////////////////////

/////////clock divider////////////////////////

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;


entity clock_divider is
    generic (divider : natural := 100_000_000); -- 1 pulse in every one second
    Port ( sys_clk : in STD_LOGIC;              -- The base frequency for Basys 3 board (xc7a35tcpg236-1 chip) is 100 MHz
           rst : in STD_LOGIC;
           clk : out STD_LOGIC);
end clock_divider;

architecture Behavioral of clock_divider is
    signal internal_clock : std_logic;
begin

    process (rst, sys_clk)
        variable clk_divider : natural;
    begin
        if (rst = '1') then
            clk_divider := 0;
            internal_clock <= '0';
        elsif(rising_edge(sys_clk)) then
            if (clk_divider < (divider / 2)) then
                clk_divider := clk_divider + 1;
                internal_clock <= '0';
            elsif (clk_divider = divider-1) then
                clk_divider := 0;
                internal_clock <= '1';
            else
                clk_divider := clk_divider + 1;
                internal_clock <= '1';
            end if;
        end if;
    end process;

    clk <= internal_clock;

end Behavioral;
///////////////////////////////////////

////////////comparator //////////////

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparator is
    generic ( width : positive := 3);
    Port ( A, B : in STD_LOGIC_VECTOR (width-1 downto 0);
           lt, eq, gt : out STD_LOGIC);
end comparator;

architecture Behavioral_v1 of comparator is

begin

    eq <= '1' when A = B else '0';
    lt <= '1' when A < B else '0';
    gt <= '1' when A > B else '0';

end Behavioral_v1;
/////////////////////////////////

//////////one_hot_encoder///////////

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;


entity one_hot_encoder is
    generic ( width : natural := 4);
    Port ( D : in STD_LOGIC_VECTOR (width-1 downto 0);
           Y : out STD_LOGIC_VECTOR (width-1 downto 0);
           v : out STD_LOGIC);
end one_hot_encoder;

architecture Behavioral of one_hot_encoder is

begin

    process(D)
        variable OneHot : integer := 0;
    begin
        Y <= (others => '0');
        if unsigned(D) > 0 then
            for i in width-1 downto 0 loop
                OneHot := i;
                exit when D(i) = '1';
            end loop;
            Y(OneHot) <= '1';
            v <= '1';
        else
            v <= '0';
        end if;
    end process;

end Behavioral;
/////////////////////////////////////////

/////////priority encoder //////////////

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;


entity priority_encoder is
    generic ( width : positive := 3);
    Port ( D : in STD_LOGIC_VECTOR (2**width-1 downto 0);
           Y : out STD_LOGIC_VECTOR (width-1 downto 0);
           v : out STD_LOGIC);
end priority_encoder;

architecture Behavioral of priority_encoder is

begin

    process(D)
        variable OneHot : integer := 0;
    begin

        Y <= (others => '0');
        if unsigned(D) > 0 then
            for i in 2**width-1 downto 0 loop
                OneHot := i;
                exit when D(i) = '1';
            end loop;

            Y <= std_logic_vector(to_unsigned(OneHot, width));
            v <= '1';
        else
            v <= '0';
        end if;
    end process;

end Behavioral;
////////////////////////////