Lab10 - Ej01 - Código y Testbench

module decode (
              input phase, C, Z,
              input [3:0] i,
              output [12:0] out_data);

  wire [6:0] in = {i, C, Z, phase};
  reg [12:0] out;

  always @ (in)
    begin
      casex(in)
        7'b??????0: // any
          out <= 13'b1000000001000;
        7'b00001?1: // JC, C=1
          out <= 13'b0100000001000;
        7'b00000?1: // JC, C=0
          out <= 13'b1000000001000;
        7'b00011?1: // JNC, C=1
          out <= 13'b1000000001000;
        7'b00010?1: // JNC, C=0
          out <= 13'b0100000001000;
        7'b0010??1: // CMPI
          out <= 13'b0001001000010;
        7'b0011??1: // CMPM
          out <= 13'b1001001100000;
        7'b0100??1: // LIT
          out <= 13'b0011010000010;
        7'b0101??1: // IN
          out <= 13'b0011010000100;
        7'b0110??1: // LD
          out <= 13'b1011010100000;
        7'b0111??1: // ST
          out <= 13'b1000000111000;
        7'b1000?11: // JZ, Z = 1
          out <= 13'b0100000001000;
        7'b1000?01: // JZ, Z = 0
          out <= 13'b1000000001000;
        7'b1001?11: // JNZ, Z = 1
          out <= 13'b1000000001000;
        7'b1001?01: // JNZ, Z = 0
          out <= 13'b0100000001000;
        7'b1010??1: // ADDI
          out <= 13'b0011011000010;
        7'b1011??1: // ADDM
          out <= 13'b1011011100000;
        7'b1100??1: // JMP
          out <= 13'b0100000001000;
        7'b1101??1: // OUT
          out <= 13'b0000000001001;
        7'b1110??1: // NORI
          out <= 13'b0011100000010;
        7'b1111??1: // NORM
          out <= 13'b1011100100000;
        default:
          out <= 13'b0101010101010;
      endcase
    end

    assign out_data = out;
endmodule


module testbench();
    reg phase, C, Z;
    reg [3:0] i;
    reg [6:0] test;
    wire [12:0] code;

    wire [6:0] in;

    assign in = {i, C, Z, phase}; // Esta asignación sirve para que el $monitor pueda tomar sólo 1 variable de entrada (en este caso 'in')

    decode dc(.phase(phase), .C(C), .Z(Z), .i(i), .out_data(code));

    initial begin
        $display("phase = 0;");
        phase = 0; C = 1; Z = 0; i = 4'b1010; // phase = 0
        $monitor("Input: %b Output: %b", in, code);
        #1
        $display("JC con C = 1");
        i = 4'b0000; C = 1; Z = 0; phase = 1;
        #1
        $display("JC con C = 0");
        i = 4'b0000; C = 0; Z = 0; phase = 1;
        #1
        $display("JNC con C = 0");
        i = 4'b0001; C = 0; Z = 0; phase = 1;
        #1
        $display("JNC con C = 1");
        i = 4'b0001; C = 1; Z = 0; phase = 1;
        #1
        $display("CMPI");
        i = 4'b0010; C = 1; Z = 0; phase = 1;
        #1
        $display("CMPM");
        i = 4'b0011; C = 1; Z = 0; phase = 1;
        #1
        $display("LIT");
        i = 4'b0100; C = 1; Z = 0; phase = 1;
        #1
        $display("IN");
        i = 4'b0101; C = 1; Z = 0; phase = 1;
        #1
        $display("LD");
        i = 4'b0110; C = 1; Z = 0; phase = 1;
        #1
        $display("ST");
        i = 4'b0111; C = 1; Z = 0; phase = 1;
        #1
        $display("JZ con Z = 1");
        i = 4'b1000; C = 0; Z = 1; phase = 1;
        #1
        $display("JZ con Z = 0");
        i = 4'b1000; C = 0; Z = 0; phase = 1;
        #1
        $display("JNZ con Z = 1");
        i = 4'b1001; C = 0; Z = 1; phase = 1;
        #1
        $display("JNZ con Z = 0");
        i = 4'b1001; C = 0; Z = 0; phase = 1;
        #1
        $display("ADDI");
        i = 4'b1010; C = 0; Z = 0; phase = 1;
        #1
        $display("ADDM");
        i = 4'b1011; C = 1; Z = 0; phase = 1;
        #1
        $display("JMP");
        i = 4'b1100; C = 1; Z = 1; phase = 1;
        #1
        $display("OUT");
        i = 4'b1101; C = 1; Z = 0; phase = 1;
        #1
        $display("NANDI");
        i = 4'b1110; C = 0; Z = 0; phase = 1;
        #1
        $display("NANDM");
        i = 4'b1111; C = 0; Z = 0; phase = 1;
    end

endmodule