LFSR24 (eZ80)

LFSR24:
;;ADL mode expected
;;Input: (seed1) is non-zero
;;Output: (seed1) updated, HL is the result
;;Destroys: A
;;30cc (-3cc if using SMC)
#IF smc == 0
    ld hl,(seed1)
#ELSE
seed1 = $+1
    ld hl,1
#ENDIF
    ld a,l
    add hl,hl
    rla
    and %00010111
    jp po,$+5
    inc l
    ld (seed1),hl
    ret