sine_table_controller

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-- Company:
-- Engineer:
--
-- Create Date: 01.05.2016 16:54:33
-- Design Name:
-- Module Name: sine_table_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sine_table_controller is
    Port ( clk : in STD_LOGIC;
           generate_enable : in STD_LOGIC;
           addr : out STD_LOGIC_VECTOR (12 downto 0);
           amplitude : out STD_LOGIC_VECTOR (2 downto 0));
end sine_table_controller;

architecture Behavioral of sine_table_controller is

signal cnt : std_logic_vector (10 downto 0);
signal cnt_tmp : std_logic_vector(10 downto 0);

begin
    cnt <= "00000000000";
    addr <= "0000000000000";

    amplitude <= "010";
    process(clk)
    begin
        if(generate_enable = '1') then
            addr(10 downto 0) <= cnt;
            cnt_tmp <= cnt;
            if(cnt < "10111011011") then
                cnt <= std_logic_vector( unsigned(cnt_tmp) + 1 );
            else
                cnt <= "00000000000";
            end if;
        end if;
    end process;
end Behavioral;