freq_divider_tb

`timescale 1ns / 1ps

module freq_divider_tb;

reg clock;
wire clock_out;

freq_divider freq_div (
    .clk (clock),
    .clk_out (clock_out)
);

integer i;

initial begin
    i = 0;
    clock = 0;
    for (i = 0 ; i < 30 ; i = i + 1) begin
        #5 clock = ~clock;
        #5 clock = ~clock;
    end
end
endmodule