ArmPriorityVectorFilter

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--  Prioritaetsencoder fuer das Finden des niederwertigsten
--  gesetzten Bits in einem 16-Bit-Vektor.
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--  Datum:      ??.??.2013
--  Version:    ?.??
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library ieee;
use ieee.std_logic_1164.all;

entity ArmPriorityVectorFilter is
    port(
        PVF_VECTOR_UNFILTERED   : in std_logic_vector(15 downto 0);
        PVF_VECTOR_FILTERED : out std_logic_vector(15 downto 0)
        );
end entity ArmPriorityVectorFilter;

architecture structure of ArmPriorityVectorFilter is

    component ArmRegisterBitAdd
        port(
            RBA_REGLIST : in std_logic_vector(15 downto 0);
            RBA_NR_OF_REGS  : out std_logic_vector(4 downto 0)
        );
    end component ArmRegisterBitAdd;

    signal nummer_of_regs: std_logic_vector(4 downto 0);
    signal pos: integer;

    begin

    CURRENT_NR_OF_REGS : ArmRegisterBitAdd
        port map(
            RBA_REGLIST => PVF_VECTOR_UNFILTERED;
            RBA_NR_OF_REGS  => nummer_of_regs;
        );


    process(PVF_VECTOR_UNFILTERED, nummer_of_regs)
        variable i: integer;
    begin
        for i in 15 downto 0 loop -- das niederwertigste bit = 1 finden
            if (PVF_VECTOR_UNFILTERED(i) = '1') then
                pos = i;
                exit;
            end if;
        end loop;

        case nummer_of_reg
            when "0001" => PVF_VECTOR_FILTERED <= PVF_VECTOR_UNFILTERED; --wenn ein Bit gesetzt, bleibt er gesetzt
            when "0000" => PVF_VECTOR_FILTERED <= others => '0'; --wenn kein Bit gesetzt, so gilt es auch fuer den ausgang
            when others =>
                            PVF_VECTOR_FILTERED <= others => '0';
                            PVF_VECTOR_FILTERED(pos) <= '1';
        end case;
    end process;

end architecture structure;